SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 149

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.4.3
Address Bus
DMA Address Modes
devices are explicitly addressed.
destination device. In the source read cycle, data is read from the source address and placed in the
DMAC internal Data Holding Register (DHR). Then, in the destination write cycle, the data held in the
DHR is written to the destination address.
transferred from a source device to a destination device in response to a DMA request. The transfer size
can be 32 bits, 16 bits or 8 bits.
source device to a destination device during dual-address mode.
Controller supports either 16-bit or 8-bit bus accesses for external memory. If the DMA transfer size is
programmed to 32 bits in CCRn.TrSiz, DMA read and write cycles each take up to four bus cycles to
complete. A 16-bit data bus, as programmed in the CS/Wait Controller, requires two independent bus
cycles to complete a 32-bit transfer. Likewise, an 8-bit data bus requires four independent bus cycles to
complete a 32-bit transfer.
field in addition to the setting of CCRn.TrSiz. The DPS field defines the port size of a source or
destination I/O peripheral. The I/O port size can be 32 bits, 16 bits or 8 bits.
If the I/O port size is less than the programmed transfer size, the internal 32-bit DHR serves as a buffer
for the data being transferred. For example, assume that the transfer size is programmed to 32 bits. If
the source I/O port size is 8 bits and the destination memory width is 32 bits, then four 8-bit read cycles
occur, followed by a 32-bit write cycle. (If the destination is an external memory with a 16-bit data bus,
Data Bus
The TMP1940CYAF supports only dual-address mode in which both the source and destination
In dual-address mode, two bus transfers occur: a read from a source device and a write to the
The transfer size programmed into the CCRn.TrSiz field determines the amount of data that is
The internal DHR is a 32-bit register that serves as a buffer for the data being transferred from a
Memory accesses occur in a manner to fulfill the CCRn.TrSiz setting. Remember that the CS/Wait
Memory-to-I/O and I/O-to-memory DMA transfers are governed by the setting of the CCRn.DPS
If the transfer size is equal to the I/O port size, an I/O access takes a single read or single write cycle.
Figure 10.12 Dual-Address Transfer Mode
DMAC
TMP1940CYAF-107
Address
Data
1. Source read
2. Desti. write
1. Source read
2. Desti. write
Destination Device
Source Device
TMP1940CYAF