SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 200

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.4.4
Timing and Measurement Functions Using the Capture Capability
including the following:
(1) One-Shot Pulse Generation Using an External Trigger Pulse
The capture capability of the TMRBn provides versatile timing and measurement functions,
One-shot pulse generation using an external trigger pulse
Frequency measurement
Pulse width measurement
Time difference measurement
one of the prescalar outputs. The TB0IN0 pin is used as an active-high external trigger pulse input
for latching the counter value into Capture Register 0 (TB0CP0).
programmed to generate an INT5 interrupt upon detection of a rising edge on the TB0IN0/INT5
pin. A one-shot pulse has a delay and width controlled by the values stored in the timer registers
(TB0RG0 and TB0RG1). Programming the TB0RG0 and TB0RG1 is the responsibility of the
INT5 interrupt handler. The TB0RG0 is loaded with the sum of the TB0CP0 value (c) plus the
pulse delay (d)
pulse width (p)
set to 11, so that the timer flip-flop (TB0FF0) will toggle when a match is detected between the
UC0 and the TB0RG0 and between the UC0 and the TB0RG1. With the TB0FF0 toggled twice, a
one-shot pulse is produced. Upon a match between the UC0 and the TB0RG1, the TMRB0
generates the INTTB01 interrupt, which must disable the toggle-trigger for the TB0FF0.
Counter Clock
(Internal Clock)
TB0IN0 Input Pin
(External Trigger Pulse)
TB0RG0 Match
TB0RG1 Match
TB0OUT (Timer Output) Pin
The TMRBn can be used to produce a one-time pulse as follows.
The 16-bit up-counter (UC0) is programmed to function as a free-running counter, clocked by
The TB0IN0 pin is shared with P74 and INT5. The Interrupt Controller (INTC) must be
Next, the TB0E1T1 and TB0E0T1 bits in the Timer Flip-Flop Control register (TB0FFCR) are
Figure 12.18 depicts one-shot pulse generation, with annotations showing (c), (d) and (p).
Figure 12.18 One-Shot Pulse Generation (with a Delay)
i.e., (c) + (d). The TB0RG1 is loaded with the sum of the TB0RG0 value plus the
i.e., (c) + (d) + (p).
TMP1940CYAF-158
c
Toggle is disabled for a
capture into TB0CP1.
The counter is free-running.
The UC0 value is latched into TB0CP1.
INT5 is generated.
Delay
(d)
Toggle is
enabled.
c
d
Pulse Width
Toggle is
enabled.
(p)
TMP1940CYAF
c
d
p
INTTB01 is
generated.