SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 298

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.7 SBI Timing
18.7.1
SCL clock frequency
Hold time for START condition
Low period of the SCL
clock
SCL clock high width
Setup time for a repeated START
condition
Data hold time
Data setup time
Setup time for STOP condition
Bus free time between STOP and
START conditions
Note 1: Different from the Philips I
Note 2: The ouptut data hold time is equal to 12x.
Note 3: The Philips I
Note 4: To operate the SBI in I
Note 5: Although THE I
the SDA signal to bridge the undefined region of the fall edge of SCL. However, the TMP1940CYAF SBI does
not satisfy this requirement. Also, the output buffer for SCL does not incorporate slope control of the falling
edges; therefore, the equipment manufacturer should design so that the input data hold time shown in the
table is satisfied, including tr/tf of the SCL and SDA lines.
Standard mode, the fsys frequency must be no less than 4 MHz.
obstruct the SDA and SCL lines if V
requirement.
Parameter
I
letter n denotes the value of n programmed into the SCK[2:0] (SCL output frequency select) field in the
SBI0CR1.
2
C Mode
In the table below, the letters x and T represent the fsys and T0 cycle periods, respectively. The
SDA
SCL
2
C-bus specification states that a device must internally provide a hold time of at least 300 ns for
S: START condition
Sr: Repeated START condition
P: STOP condition
Input
Output
Input
Output
2
C BUS SPECIFICATION from Philips states that I/O pins of Fast-mode devices must not
S
t
2
HD;STA
C Fast mode, the fsys frequency must be no less than 20 MHz. To operate the SBI in I
Symbol
t
t
t
t
t
t
t
t
t
t
f
SC
HD:STA
LOW
HIGH
SU;STA
HD;DAT
SU;DAT
SU;STO
BUF
2
C-bus specification.
t
LOW
t
SU;DAT
(2
dependent
dependent
Software-
Software-
TMP1940CYAF-256
t
(n 1)
SCL
2
Min
(n 1)
t
r
Equation
0
DD
T
4) T
t
HIGH
is switched off, the TMP1940CYAF does not comply with this
Max
t
HD;DAT
fsys
4 (Note 1)
Standard Mode
Min
250
4.0
4.7
4.0
4.7
4.0
4.7
0
6
0
8 MHz, n
Max
100
t
SU;STA
Sr
4
TMP1940CYAF
fsys
1 (Note 1)
Min
100
0.6
1.3
0.6
1.5
0.6
0.6
1.3
0
0
Fast Mode
32 MHz, n
t
SU;STO
P
Max
400
t
BUF
4
Unit
kHz
ns
2
s
s
s
s
s
s
s
s
s
C