PACCLK5406D-S-EVN Lattice, PACCLK5406D-S-EVN Datasheet - Page 8

• Manufacturer Part Number: PACCLK5406D-S-EVN
• Description: Development Software ispClock5312S Eval 56020A Dev Mix Sig
• Manufacturer: Lattice

Specifications of PACCLK5406D-S-EVN

• Tool Type: Development Software Support
• Core Architecture: CPLD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 7. Scope Plot - Bank 0 and Bank 2 Overlapped
2. In PAC-Designer choose Tools > Design Utilities…
3. Choose ispPAC-CLK54_Skew_Editor.exe and click OK.
Figure 8. ispPAC-CLK5406D Skew Editor
Note that a small inherent skew of the outputs plus any set-up delay in cables is about 50-80ps.
The Design Utilities dialog appears.
The ISPPAC-CLK5406D Skew Editor appears.
The Skew Editor allows you to graphically configure the ispClock5406D output skew. Waveforms are color
coded. All disabled outputs are indicated in gray, while active outputs are indicated in green or white. Skew is
adjusted by dragging the waveform edges with the mouse. Dragging the waveform specified as feedback (high-
lighted in green) will move every other waveform in the opposite direction.
The Phase Skew steps are larger steps than the Time Skew. In the demo design, the “PUD” Phase Unit Delay,
has steps of 0.31 ns and there are 16 steps for each bank. For the demo, the Time Skew step is 18 ps.
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ispClock5400D Evaluation Board
User’s Guide