PACCLK5406D-S-EVN Lattice, PACCLK5406D-S-EVN Datasheet - Page 15

• Manufacturer Part Number: PACCLK5406D-S-EVN
• Description: Development Software ispClock5312S Eval 56020A Dev Mix Sig
• Manufacturer: Lattice

Specifications of PACCLK5406D-S-EVN

• Tool Type: Development Software Support
• Core Architecture: CPLD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
8. Click the Change… button until the Uses PC USB Port title appears.
9. Disable the Bypass Hardware Checking (Demo Mode) option.
10. Click the Settings… button.
11. From the Select USB port name… section, choose Search for download cable on all USB ports and click
12. From the Cable and I/O Port Setup dialog, click OK.
13. From the ispClock5406D I
Figure 16. ispClock5406D I
14. Select 7Fh from the I
To apply an in-system output change:
1. If you have not done so, connect the evaluation board to a scope and adjust the display using the procedure in
2. Adjust the scope to display BANK0_P and BANK2_P signals only. Overlap the signals to compare the relative
The USB Settings dialog appears.
Connect Now.
The I
The ispClock5406 I
The I
The 5406D I
loaded with the JTAG pattern. Once the address is set, full communication can be established with the device
using the I
Note: Make sure the ispDOWNLOAD cable is moved to the I
the Modify Clock Time Skew section of this document.
skew.
2
2
C utility indicates when the USB connection is made. Click OK.
C Utility sets the I
2
C interface.
2
C device address must match what is stored in E
2
C Address dialog appears.
2
C Address list and click OK.
2
C address for the ispClock5406D.
2
C Address Dialog Box
2
C Utility click the I
2
C Address = … button.
15
2
C port header J15 on the evaluation board.
2
CMOS when the device program was down-
ispClock5400D Evaluation Board
User’s Guide