PACCLK5406D-S-EVN Lattice, PACCLK5406D-S-EVN Datasheet - Page 6

• Manufacturer Part Number: PACCLK5406D-S-EVN
• Description: Development Software ispClock5312S Eval 56020A Dev Mix Sig
• Manufacturer: Lattice

Specifications of PACCLK5406D-S-EVN

• Tool Type: Development Software Support
• Core Architecture: CPLD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
9. If the board is not programmed with the demo project yet, press the Download icon on the top toolbar.
Figure 4. PAC-Designer Top Toolbar
Figure 5. Frequency Summary Dialog Box
10. Click OK.
11. Attach high-speed scope leads to the SMA sockets at BANK0 P, N and BANK2 P, N.
12. Set the scope input channel settings to 50 Ohm termination.
The Frequency Summary dialog appears and reports the Reference and VCO frequency settings.
PAC-Designer reprograms the evaluation board with the updated JEDEC programming file.
For this mode, we use LVDS and the 50 Ohm termination on each scope channel.
The waveforms shown are using 3’ long RG-316 cables with the SMA connectors. If the equipment has high
impedance probes or a differential probe, make sure that the LVDS BANK outputs have 100 Ohm termination
from BANK_P to BANK_N.
When operating properly, you should see four waveforms on the scope as shown in Figure 6. This represents
BANK0 and BANK2 output waveforms for both the BANK_P and BANK_N on each respectively. BANK0_P,N
are shown on the top pair, BANK2_P,N are shown on bottom pair. The full differential output would equal:
[BANK0_P minus BANK0_N] as well as on BANK2.
See the tables in the schematic (Appendix A) showing termination resistor options.
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ispClock5400D Evaluation Board
User’s Guide