PACCLK5406D-S-EVN Lattice, PACCLK5406D-S-EVN Datasheet - Page 13

• Manufacturer Part Number: PACCLK5406D-S-EVN
• Description: Development Software ispClock5312S Eval 56020A Dev Mix Sig
• Manufacturer: Lattice

Specifications of PACCLK5406D-S-EVN

• Tool Type: Development Software Support
• Core Architecture: CPLD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 13. Scope Plot - 156.25 MHz Output
The 156.25 MHz clock from the REFB input output appears on the scope.
6. Toggle position 3 of the DIP switch (USER3) on the evaluation board back to the 1=REF-SEL position to
In-System Changes via I
This section demonstrates the I
ture allows you to override many device parameters of the device programming and make in-system changes to
almost all phase, time, reference and frequency settings of the ispClock5406D. The feature allows dynamic
time/phase skew for testing and margining of the output clocks, on every bank output pair. Upon device reset the
device returns to the configuration stored in E
The PAC-Designer I
registers such as output group and PLL controls.
The demo will apply all the changes you performed by reprogramming the device in the earlier procedures of the
user’s guide.
To set up the I
1. If you have not done so already, connect the ispDOWNLOAD cable to the I
2. Start PAC-Designer.
3. Choose File > Open…
4. Browse the Base_Demo_CLK5406.PAC project and choose Open.
5. From PAC-Designer choose Tools > Design Utilities…
enable the 100 MHz input reference clock, REFA_P/N input.
Figure 41).
The Open dialog appears. (Note for PAC-Designer 5.2: See the Troubleshooting section of this user’s guide for
information on a correction required prior to using the I
The ispPAC-CLK5406D schematic view appears.
The Design Utilities dialog appears.
2
C ispDOWNLOAD Cable interface:
2
C Design Utility for the ispClock5406D provides a software interface to the ispClock5406D I
2
C Bus Interface
2
C status and control interface to the ispClock5406D device. The I

2
CMOS.
13
2
C Design Utility.)
ispClock5400D Evaluation Board
2
C pin header (Appendix A,
User’s Guide
2
C interface fea-
2
C