PACCLK5406D-S-EVN Lattice, PACCLK5406D-S-EVN Datasheet - Page 12

• Manufacturer Part Number: PACCLK5406D-S-EVN
• Description: Development Software ispClock5312S Eval 56020A Dev Mix Sig
• Manufacturer: Lattice

Specifications of PACCLK5406D-S-EVN

• Tool Type: Development Software Support
• Core Architecture: CPLD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 12. Scope Plot - Phase Skew Adjustment
Modify the Reference Clock Source Input
The evaluation board provides both 100 MHz (REFA) and 156.25 MHz (REFB) reference clock sources using on-
board CMOS oscillators. This section demonstrates active clock selection using the ispClock5406D user-program-
mable control and status USER pins, to adjust the on-chip REFSEL signal. In this case, the user signal input
(USER3) acts as a mux control over REFA and REFB input reference clocks.
To modify the reference clock source input:
1. From PAC-Designer, double-click the USER Signal Routing Block.
2. Note the REFSEL function input is set to the USER3 pin input.
3. Click Cancel.
4. Toggle position 3 of the DIP switch (USER3) on the evaluation board to the 0= (zero) position to enable the
5. Note the updated scope display.
The waveform shows the BANK_2 output advanced 1.24 ns.
The USER Pin Function Allocation dialog appears.
This allows an external control over the ispClock5406D reference clock source input path.
156.25 MHz input reference clock, REFB_P/N input.
12
ispClock5400D Evaluation Board
User’s Guide