PACCLK5406D-S-EVN Lattice, PACCLK5406D-S-EVN Datasheet - Page 4

• Manufacturer Part Number: PACCLK5406D-S-EVN
• Description: Development Software ispClock5312S Eval 56020A Dev Mix Sig
• Manufacturer: Lattice

Specifications of PACCLK5406D-S-EVN

• Tool Type: Development Software Support
• Core Architecture: CPLD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Hardware Requirements
The following hardware is recommended for evaluation and demonstrations:
• Four matched SMA cables, SMA-to-BNC, 6 inches to 3 feet in length
• ESD strap or proper ESD test environment
• ispClock5400D Evaluation Board
• Lattice ispDOWNLOAD Cable
• AC wall adaptor for 5V DC output
• Optional: LatticeECP3 Serial Protocol Board (LFE3-95EA-SP-EVN)
• Optional: LatticeECP3 Video Protocol Board (LFE3-95EA-V-EVN)
• Optional: BERT Analyzer
• Optional: Agilent 8133A Clock Generator
• Optional: 4-channel, high-speed oscilloscope
Demonstration Designs
A common application of the ispClock5406D and a low-cost CMOS oscillator is to provide a low-jitter clock source
for SERDES-based applications in high-performance communications and computing equipment. The evaluation
board includes three demos that illustrate key applications of the ispClock5406D in the context of clock distribution
applications:
• ispClock5406D Base Demo – A pre-programmed, base demo of ispClock5406D features: low-jitter, time/phase
• Period Jitter Measurement – A demonstration of how to connect and measure ispClock5400D period jitter per-
• SERDES Reference Clock – A co-demonstration with the LatticeECP3 Serial Protocol or I/O Protocol boards.
• Video Reference Clock – A co-demonstration with the LatticeECP3 Video Protocol board.
Note: It is possible that you will obtain your evaluation board after it has been reprogrammed. To restore the factory
default demo and program it with other Lattice-supplied examples, see the Download Demo Designs section of this
document.
Base Demo of the ispClock5406D
The base demo consists of setting up the ispClock5400D Evaluation Board hardware and test equipment to dem-
onstrate key features of the ispClock5406D device. The ability to adjust skew and frequency will be demonstrated
as well as programmable frequency, time and phase delay, reset functions and full dynamic control of internal reg-
isters through the on-board I
Monitoring Clock Outputs
This section describes the procedure to monitor the evaluation board’s Bank 0 and Bank 2 clock outputs with a dig-
ital oscilloscope. Both banks are configured for LVDS output types.
To monitor clock outputs:
1. If you have not done so already, see the Programming the ispClock5400D Evaluation Board with ispVM section
skew output control and I
formance with a signal integrity analyzer.
of this document for details on set-up for the programming cable and applying power to the evaluation board.
2
C interface.
2
C bus interface.
4
ispClock5400D Evaluation Board
User’s Guide