PACCLK5406D-S-EVN Lattice, PACCLK5406D-S-EVN Datasheet - Page 24

• Manufacturer Part Number: PACCLK5406D-S-EVN
• Description: Development Software ispClock5312S Eval 56020A Dev Mix Sig
• Manufacturer: Lattice

Specifications of PACCLK5406D-S-EVN

• Tool Type: Development Software Support
• Core Architecture: CPLD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 25. Frequency Summary Dialog Box
4. Click OK.
ispClock5400D Evaluation Board
This section describes the features of the ispClock5400D Evaluation Board in detail. The features appear in alpha-
betical order.
DIP Switch
To simplify the use of the evaluation board an 8-position DIP switch (SW1) is provided for common adjustments.
The switch can be roughly divided into four sections: reference oscillator control, PLL control, output enables, and
VCCO control. Table lists the switches and their respective functions. Note that for switch sections 6, 7, and 8 only
one should be on at a time. The default setting with all the switches to the left (OFF) enables the on-board oscilla-
tor, selects that as the clock reference, and allows the PLL to lock to that frequency.
Table 1.
Input/Output Connections
The evaluation board incorporates tapered transitions from the SMA connectors to the matched 50-ohm microstrip
transmission lines. All of the output transmission lines are matched in length to the sense signals (REFA, REFB,
and FEEDBACK) to support accurate timing measurements both for bank-to-bank and input-to-output. The header
at J16 (Appendix A, Figure 41) provides access to the essential control and monitor pins of the ispClock5406D
such as REFA_EN, REFB_EN, USER0, USER3, REFB_VTT, VCCO, and FBK_VTT.
Off-Board Clock Connections
An off-board CMOS clock can be used by connecting to the REFB_P (J2) SMA connector (Appendix A, Figure 35).
When using a CMOS reference clock, the negative differential input must be biased to VCC/2. For REF_B this is
done by populating R5, R7, and C53.
PAC-Designer reprograms the evaluation board with the updated JEDEC programming file.
DIP Switch Functions
To the Left
LOCK-LED
Unused
2.5V
1.8V
1.5V
0=
0=
0=
SW1 – Section
1
2
3
4
5
6
7
8
24
ispClock5400D Evaluation Board
To the Right
1=REFB_EN
1=REFA_EN
N/C=USER0
1=REF-SEL
Unused
3.3V
3.3V
3.3V
User’s Guide