PACCLK5406D-S-EVN Lattice, PACCLK5406D-S-EVN Datasheet - Page 18

• Manufacturer Part Number: PACCLK5406D-S-EVN
• Description: Development Software ispClock5312S Eval 56020A Dev Mix Sig
• Manufacturer: Lattice

Specifications of PACCLK5406D-S-EVN

• Tool Type: Development Software Support
• Core Architecture: CPLD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 20. ispClock5406D Soft Reset Dialog - Soft Reset Released State
4. Click OK.
5. Click the Full Reset button.
6. Click OK.
7. Click the Full Reset button.
8. Click OK.
You have completed the ispClock5406D Base Demo. You can try other in-system device configurations using the
I
Period Jitter Measurement
The demo consists of setting up the ispClock5400D Evaluation Board hardware and a Wavecrest (Gigamax) SIA-
3000D analyzer to demonstrate the ultra-low phase jitter of the ispClock5406D device.
How to set up the SIA-3000D:
1. From the SIA-3000D, GigaView software, perform Extended Timer Calibration (>=11min calibration).
2. Open the Clock Analysis Tool and set up for a Period Jitter measurement.
Set up the base demo project for a phase jitter measurement:
1. Use PAC-Designer to open the Base_Demo_CLK5406D.PAC project.
2. Save the Base_Demo_CLK5406D.PAC as Base_Demo_CLK5406D_jitter.pac.
3. Choose Edit > Symbol...
4. Choose REF Frequency and click Edit...
2
C utility or modify the PAC-Designer project then reprogram the device.
Note the scope display changes to reflect the time-skewed waveform pattern produced earlier. I
will be retained and reapplied after soft reset has been released.
The ispClock5406D Full Reset dialog prompt appears and the I
reset. During this state, all configuration registers are updated from the E
loaded by I
device. The differential outputs of the ispClock5406D banks are disabled during the full reset state.
The ispClock5406D Full Reset dialog prompt appears and the I
reset. When released from a full reset the device reverts back to the configuration state that is defined and
stored in E
Note the scope display changes to reflect the original waveform pattern produced by the initial ispClock5406D
device programming.
The Edit Symbol dialog appears.
The PLL Core Settings dialog appears.
2
2
CMOS.
C are overwritten. This command is equivalent to toggling the RESETb pin of the ispClock5406D
18
2
2
C utility issues the I
C utility issues the I
ispClock5400D Evaluation Board
2
CMOS configuration. All the values
2
2
C command to release full
C command to assert full
User’s Guide
2
C commands