PACCLK5406D-S-EVN Lattice, PACCLK5406D-S-EVN Datasheet - Page 11

• Manufacturer Part Number: PACCLK5406D-S-EVN
• Description: Development Software ispClock5312S Eval 56020A Dev Mix Sig
• Manufacturer: Lattice

Specifications of PACCLK5406D-S-EVN

• Tool Type: Development Software Support
• Core Architecture: CPLD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 11. Scope Plot - Inverted Output Bank
6. Repeat steps 1-4 to adjust the output bank to not invert the output (Inverted = No) and reprogram the device.
Modify Clock Phase Skew
This section describes the procedure to modify phase skew of the ispClock5406D output. The Phase skew Unit
Delay (PUD) is 0.31 ns for the demo design. In the following procedure the phase skew will be advanced four PUD
units or 1.24 ns.
To modify clock phase skew:
1. From PAC-Designer choose Edit > Symbol…
2. Choose Skew Manager and click the Edit… button
3. Choose the following options:
4. Click the Download icon on the top toolbar.
5. Click OK.
6. Note the updated scope display.
The Edit Symbol dialog appears.
Phase Skew Manager appears.
PAC-Designer updates the phase skew for the project.
The Frequency Summary dialog appears and reports the Reference and VCO frequency settings.
PAC-Designer reprograms the evaluation board with the updated JEDEC programming file.
Skew Step = Fine
BANK_2 Phase Skew = 4PUD
Click OK.
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ispClock5400D Evaluation Board
User’s Guide