IP-AGX-PCIE/1 Altera, IP-AGX-PCIE/1 Datasheet - Page 77

• Manufacturer Part Number: IP-AGX-PCIE/1
• Description: IP CORE - X1 Lane PCI Express For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 4: IP Core Architecture
PCI Express Avalon-MM Bridge
December 2010 Altera Corporation
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To improve PCI Express throughput, Altera recommends using an Avalon-MM burst
master without any byte-enable restrictions.
Avalon-MM-to-PCI Express Upstream Read Requests
The PCI Express Avalon-MM bridge converts read requests from the system
interconnect fabric to PCI Express read requests with 32-bit or 64-bit addresses based
on the address translation configuration, the request address, and maximum read
size.
The Avalon-MM TX slave interface can receive read requests with burst sizes of up to
4 KBytes sent to any address. However, the bridge limits read requests sent to the PCI
Express link to a maximum of 256 bytes. Additionally, the bridge must prevent each
PCI Express read request packet from crossing a 4 KByte address boundary.
Therefore, the bridge may split an Avalon-MM read request into multiple PCI Express
read packets based on the address and the size of the read request.
For Avalon-MM read requests with a burst count greater than one, all byte enables
must be asserted. There are no restrictions on byte enable for Avalon-MM read
requests with a burst count of one. An invalid Avalon-MM request can adversely
affect system functionality, resulting in a completion with abort status set. An
example of an invalid request is one with an incorrect address.
PCI Express-to-Avalon-MM Read Completions
The PCI Express Avalon-MM bridge returns read completion packets to the initiating
Avalon-MM master in the issuing order. The bridge supports multiple and
out-of-order completion packets.
PCI Express-to-Avalon-MM Downstream Write Requests
When the PCI Express Avalon-MM bridge receives PCI Express write requests, it
converts them to burst write requests before sending them to the system interconnect
fabric. The bridge translates the PCI Express address to the Avalon-MM address space
based on the BAR hit information and on address translation table values configured
during the IP core parameterization. Malformed write packets are dropped, and
therefore do not appear on the Avalon-MM interface.
For downstream write and read requests, if more than one byte enable is asserted, the
byte lanes must be adjacent. In addition, the byte enables must be aligned to the size
of the read or write request.
PCI Express-to-Avalon-MM Downstream Read Requests
The PCI Express Avalon-MM bridge sends PCI Express read packets to the system
interconnect fabric as burst reads with a maximum burst size of 512 bytes. The bridge
converts the PCI Express address to the Avalon-MM address space based on the BAR
hit information and address translation lookup table values. The address translation
lookup table values are user configurable. Unsupported read requests generate a
completer abort response.
PCIe IP cores using the Avalon-ST interface can handle burst reads up to the specified
Maximum Payload Size.
The Avalon-MM byte enable may deassert, but only in the last qword of the burst.
PCI Express Compiler User Guide
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