IP-AGX-PCIE/1 Altera, IP-AGX-PCIE/1 Datasheet - Page 236

• Manufacturer Part Number: IP-AGX-PCIE/1
• Description: IP CORE - X1 Lane PCI Express For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

15–8
Figure 15–3. Top-Level Chaining DMA Example for Simulation
Note to
(1) For a description of the DMA write and read registers, refer to
PCI Express Compiler User Guide
DMA Write
DMA Control/Status Register
Figure
DMA Rd Cntl (0x10-1C)
DMA Wr Cntl (0x0-4)
Chaining DMA
Endpoint Memory
Avalon-MM
interfaces
RC Slave
15–3:
DMA Read
Figure 15–3
RC CPU.
The block diagram contains the following elements:
■
■
■
■
Endpoint DMA write and read requester modules.
The chaining DMA design example connects to the Avalon-ST interface of the PCI
Express IP core when in Avalon-ST mode, or to the ICM when in descriptor/data
mode. (Refer to
Examples). The connections consist of the following interfaces:
■
■
■
■
The descriptor tables of the DMA read and the DMA write are located in the BFM
shared memory.
A RC CPU and associated PCI Express PHY link to the endpoint design example,
using a root port and a north/south bridge.
The Avalon-ST RX receives TLP header and data information from the PCI
Express IP core
The Avalon-ST TX transmits TLP header and data information to the PCI
Express IP core
The Avalon-ST MSI port requests MSI interrupts from the PCI Express IP core
The sideband signal bus carries static information such as configuration
information
Configuration
Avalon-ST
shows a block diagram of the design example connected to an external
Appendix C, Incremental Compile Module for Descriptor/Data
MegaCore
Table 15–5 on page
Function
Variation
Express
PCI
(Note 1)
15–14.
PCI Express
Chapter 15: Testbench and Design Example
December 2010 Altera Corporation
Descriptor
Read
Table
Root Complex
Chaining DMA Design Example
Memory
Root Port
Data
CPU
Descriptor
Write
Table