IP-AGX-PCIE/1 Altera, IP-AGX-PCIE/1 Datasheet - Page 269
![IP CORE - X1 Lane PCI Express For Arria GX](/photos/24/19/241936/4696145_sml.jpg)
IP-AGX-PCIE/1
Manufacturer Part Number
IP-AGX-PCIE/1
Description
IP CORE - X1 Lane PCI Express For Arria GX
Manufacturer
Altera
Datasheet
1.IP-AGX-PCIE1.pdf
(362 pages)
Specifications of IP-AGX-PCIE/1
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Cyclone II, HardCopy II, Stratix II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
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Chapter 15: Testbench and Design Example
BFM Procedures and Functions
Table 15–33. Constants: VHDL Subtype NATURAL or Verilog HDL Type INTEGER
Table 15–34. shmem_write VHDL Procedure or Verilog HDL Task
Table 15–35. shmem_read Function
December 2010 Altera Corporation
SHMEM_FILL_ZEROS
SHMEM_FILL_BYTE_INC
SHMEM_FILL_WORD_INC
SHMEM_FILL_DWORD_INC
SHMEM_FILL_QWORD_INC
SHMEM_FILL_ONE
Location
Syntax
Arguments
Location
Syntax
Arguments addr
Return
Constant
altpcietb_bfm_shmem.v or altpcietb_bfm_shmem.vhd
leng
data
altpcietb_bfm_shmem.v or altpcietb_bfm_shmem.vhd
shmem_write(addr, data, leng)
addr
data
leng
data:= shmem_read(addr, leng)
Shared Memory Constants
The following constants are defined in the BFM shared memory package. They select
a data pattern in the shmem_fill and shmem_chk_ok routines. These shared memory
constants are all VHDL subtype natural or Verilog HDL type integer.
shmem_write
The shmem_write procedure writes data to the BFM shared memory.
shmem_read Function
The shmem_read function reads data to the BFM shared memory.
Length, in bytes, of data read
Data read from BFM shared memory.
In VHDL, this is an unconstrained std_logic_vector, in which the vector is 8 times the
leng length. In Verilog, this parameter is implemented as a 64-bit vector. leng is 1- 8 bytes.
If leng is less than 8 bytes, only the corresponding least significant bits of the returned data
are valid.
In both languages, bits 7 downto 0 are read from the location specified by addr; bits 15
downto 8 are read from the addr+1 location, etc.
BFM shared memory starting address for reading data
BFM shared memory starting address for writing data
Data to write to BFM shared memory.
In VHDL, this argument is an unconstrained std_logic_vector. This vector must be 8
times the leng length. In Verilog, this parameter is implemented as a 64-bit vector. leng is
1–8 bytes. In both languages, bits 7 downto 0 are written to the location specified by addr;
bits 15 downto 8 are written to the addr+1 location, etc.
Length, in bytes, of data written
Specifies a data pattern of all zeros
Specifies a data pattern of incrementing 8-bit bytes (0x00, 0x01, 0x02, etc.)
Specifies a data pattern of incrementing 16-bit words (0x0000, 0x0001, 0x0002, etc.)
Specifies a data pattern of incrementing 32-bit dwords (0x00000000, 0x00000001,
0x00000002, etc.)
Specifies a data pattern of incrementing 64-bit qwords (0x0000000000000000,
0x0000000000000001, 0x0000000000000002, etc.)
Specifies a data pattern of all ones
Description
PCI Express Compiler User Guide
15–41
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