IP-AGX-PCIE/1 Altera, IP-AGX-PCIE/1 Datasheet - Page 175
![IP CORE - X1 Lane PCI Express For Arria GX](/photos/24/19/241936/4696145_sml.jpg)
IP-AGX-PCIE/1
Manufacturer Part Number
IP-AGX-PCIE/1
Description
IP CORE - X1 Lane PCI Express For Arria GX
Manufacturer
Altera
Datasheet
1.IP-AGX-PCIE1.pdf
(362 pages)
Specifications of IP-AGX-PCIE/1
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Cyclone II, HardCopy II, Stratix II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
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Chapter 7: Reset and Clocks
Clocks
December 2010 Altera Corporation
The system interconnect fabric drives the additional input clock, clk in
the PCI Express IP core. In general, clk is the main clock of the SOPC Builder system
and originates from an external clock source.
Figure 7–12. SOPC Builder - Separate Clock Domains
Note to
(1) clk connects to Avalon-MM global clock, AvlClk_L.
If you turn on the
make appropriate clock assignments for all Avalon-MM components.
illustrates a system that uses a single clock domain.
Figure 7–13. Connectivity for a PCI Express IP core with a Single Clock Domain
Figure
7–12:
Avalon
Avalon
MM
MM
Use PCIe core clock,
clk
option for the Avalon clock domain, you must
clk125_out
clk
PCI Express
Avalon-MM
MegaCore
PCI Express Compiler User Guide
Figure 7–13
Figure
ref_clk
7–12, to
7–15
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