IP-AGX-PCIE/1 Altera, IP-AGX-PCIE/1 Datasheet - Page 170

• Manufacturer Part Number: IP-AGX-PCIE/1
• Description: IP CORE - X1 Lane PCI Express For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

7–10
PCI Express Compiler User Guide
Avalon-ST Interface—Soft IP Implementation
core_clk, core_clk_out
The core_clk signal is derived from p_clk. The core_clk_out signal is derived from
core_clk.
core_clk_out to meet PCI Express link bandwidth constraints. An asynchronous
FIFO in the adapter decouples the core_clk and pld_clk clock domains.
Table 7–1. core_clk_out Values for All Parameterizations
pld_clk
The application layer and part of the adapter use this clock. Ideally, the pld_clk drives
all user logic within the application layer, including other instances of the PCI Express
IP core and memory interfaces. The pld_clk input clock pin is typically connected to
the core_clk_out output clock pin.
The soft IP implementation of the PCI Express IP core uses one of several possible
clocking configurations, depending on the PHY (external PHY, Arria GX, Arria II GX,
Cyclone IV GX, HardCopy IV GX, Stratix II GX, Stratix IV GX, or Stratix V GX) and
the reference clock frequency. There are two clock input signals: refclk and either
clk125_in for x1 or ×4 variations or clk250_in for ×8 variations.
The ×1 and ×4 IP cores also have an output clock, clk125_out, that is a 125 MHz
transceiver clock. For external PHY variations clk125_out is driven from the refclk
input. The ×8 IP core has an output clock, clk250_out, that is the 250 MHz transceiver
clock output.
The input clocks are used for the following functions:
■
■
Note to
(1) This mode saves power.
Link Width
refclk— For generic PIPE PHY implementations, refclk is driven directly to
clk125_out.
clk125_in—This signal is the clock for all of the ×1 and ×4 IP core registers, except
for a small portion of the receive PCS layer that is clocked by a recovered clock in
internal PHY implementations. All synchronous application layer interface signals
are synchronous to this 125 MHz clock. In generic PIPE PHY implementations,
clk125_in must be connected to the pclk signal from the PHY.
×1
×1
×4
×8
×8
×1
×4
×4
×8
Table
Table 7–1
7–1:
Max Link Rate
Gen1
Gen1
Gen1
Gen1
Gen1
Gen2
Gen2
Gen2
Gen2
outlines the frequency requirements for core_clk and
Avalon-ST Width
128
128
128
64
64
64
64
64
64
62.5 MHz
core_clk
125 MHz
125 MHz
250 MHz
250 MHz
125 MHz
250 MHz
250 MHz
500 MHz
December 2010 Altera Corporation
Chapter 7: Reset and Clocks
core_clk_out
62.5 MHz
125 MHz
125 MHz
250 MHz
125 MHz
125 MHz
250 MHz
125 MHz
250 MHz
(1)
Clocks