IP-AGX-PCIE/1 Altera, IP-AGX-PCIE/1 Datasheet - Page 255

• Manufacturer Part Number: IP-AGX-PCIE/1
• Description: IP CORE - X1 Lane PCI Express For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 15: Testbench and Design Example
Root Port BFM
December 2010 Altera Corporation
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All of the files for the BFM are generated by the MegaWizard interface in the
<variation name>_examples/common/testbench directory.
BFM Configuration Procedures/Functions (altpcietb_bfm_configure VHDL
package or Verilog HDL include file)—These procedures and functions provide
the BFM calls to request configuration of the PCI Express link and the endpoint
configuration space registers. For details on these procedures and functions, see
“BFM Configuration Procedures” on page
BFM Log Interface (altpcietb_bfm_log VHDL package or Verilog HDL include
file)—The BFM log interface provides routines for writing commonly formatted
messages to the simulator standard output and optionally to a log file. It also
provides controls that stop simulation on errors. For details on these procedures,
see
BFM Request Interface (altpcietb_bfm_req_intf VHDL package or Verilog HDL
include file)—This interface provides the low-level interface between the
altpcietb_bfm_rdwr and altpcietb_bfm_configure procedures or functions and
the root port RTL Model. This interface stores a write-protected data structure
containing the sizes and the values programmed in the BAR registers of the
endpoint, as well as, other critical data used for internal BFM management. You do
not need to access these files directly to adapt the testbench to test your endpoint
application.
The root port BFM included with the PCI Express Compiler is designed to test just
one PCI Express IP core at a time. When using the SOPC Builder design flow, in
order to simulate correctly, you should comment out all but one of the PCI Express
Compiler testbench modules, named <variation_name>_testbench, in the SOPC
Builder generated system file. These modules are instantiated near the end of the
system file. You can select which one to use for any given simulation run.
Root Port RTL Model (altpcietb_bfm_rp_top_x8_pipen1b VHDL entity or Verilog
HDL Module)—This is the Register Transfer Level (RTL) portion of the model.
This model takes the requests from the above modules and handles them at an
RTL level to interface to the PCI Express link. You do not need to access this
module directly to adapt the testbench to test your endpoint application.
VC0:3 Interfaces (altpcietb_bfm_vc_intf)—These interface modules handle the
VC-specific interfaces on the root port interface model. They take requests from
the BFM request interface and generate the required PCI Express transactions.
They handle completions received from the PCI Express link and notify the BFM
request interface when requests are complete. Additionally, they handle any
requests received from the PCI Express link, and store or fetch data from the
shared memory before generating the required completions.
Root port interface model(altpcietb_bfm_rpvar_64b_x8_pipen1b)—This is an IP
functional simulation model of a version of the IP core specially modified to
support root port operation. Its application layer interface is very similar to the
application layer interface of the IP core used for endpoint mode.
“BFM Log and Message Procedures” on page
15–39.
15–43.
PCI Express Compiler User Guide
15–27