AD9547/PCBZ Analog Devices Inc, AD9547/PCBZ Datasheet - Page 73

• Manufacturer Part Number: AD9547/PCBZ
• Description: Clock Generator/Synchronizer Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9547/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9547
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9547
• Primary Attributes: 2 Differential or 4 Single Ended Inputs
• Secondary Attributes: CMOS, LVPECL & LVDS Compatible
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 62. Incremental Closed-Loop Phase Lock Offset Step Size
Address
0x0314
0x0315
1
Table 63. Phase Slew Rate Limit
Address
0x0316
0x0317
1
Table 64. History Accumulation Timer
Address
0x0318
0x0319
0x031A
1
Table 65. History Mode
Address
0x031B
The default incremental closed loop phase lock offset step size value is 0x03E8 = 1000 (1 ns).
The default phase slew rate limit is 0 (or disabled).
Do not program a timer value of 0. The history accumulation timer default value is 0x007530 = 30,000 (30 sec).
Bit
[7:0]
[7:0]
Bit
[7:0]
[7:0]
Bit
[7:0]
[7:0]
[7:0]
Bit
[7:5]
4
3
[2:0]
Bit Name
Incremental phase lock offset
step size (expressed in ps/step)
Bit Name
Phase slew rate limit
(expressed in ns/sec)
Bit Name
History accumulation timer
(expressed in ms)
Bit Name
Unused
Single sample fallback
Persistent history
Incremental average
1
1
Description
History accumulation timer, Bits[7:0].
History accumulation timer, Bits[15:8].
History accumulation timer, Bits[23:16].
Description
Incremental phase lock offset step size, Bits[7:0].
Incremental phase lock offset step size, Bits[15:8].
Description
Phase slew rate limit, Bits[7:0].
Phase slew rate limit, Bits[15:8].
Description
Unused.
Controls the holdover history. If tuning word history is not available for the
reference that was active just prior to holdover, then
Controls the holdover history initialization. When switching to a new reference
History mode value from 0 to 7 (default = 0).
0 (default) = use the free-running frequency tuning word register value.
1 = use the last tuning word from the DPLL.
0 (default) = clear the tuning word history.
1 = retain the previous tuning word history.
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