AD9547/PCBZ Analog Devices Inc, AD9547/PCBZ Datasheet - Page 7

• Manufacturer Part Number: AD9547/PCBZ
• Description: Clock Generator/Synchronizer Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9547/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9547
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9547
• Primary Attributes: 2 Differential or 4 Single Ended Inputs
• Secondary Attributes: CMOS, LVPECL & LVDS Compatible
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REFERENCE INPUTS (REFA/REFAA, REFB/REFBB)
Table 8.
Parameter
DIFFERENTIAL OPERATION
SINGLE-ENDED OPERATION
REFERENCE MONITORS
Table 9.
Parameter
REFERENCE MONITOR
TIMERS
1
f
REF
Frequency Range
Minimum Input Slew Rate
Common-Mode Input Voltage
Differential Input Voltage
Input Resistance
Input Capacitance
Minimum Pulse Width High
Minimum Pulse Width Low
Frequency Range (CMOS)
Minimum Input Slew Rate
Input Voltage High (V
Input Voltage Low (V
Input Resistance
Input Capacitance
Minimum Pulse Width High
Minimum Pulse Width Low
Loss of Reference Detection Time
Frequency Out-of-Range Limits
Validation Timer
Redetect Timer
is the frequency of the active reference; R is the frequency division factor determined by the R divider.
Sinusoidal Input
LVPECL Input
LVDS Input
Sensitivity
1.2 V to 1.5 V Threshold Setting
1.8 V to 2.5 V Threshold Setting
3.0 V to 3.3 V Threshold Setting
1.2 V to 1.5 V Threshold Setting
1.8 V to 2.5 V Threshold Setting
3.0 V to 3.3 V Threshold Setting
IL
IH
)
)
Min
10
0.001
0.001
40
620
620
0.001
40
0.9
1.2
1.9
1.5
1.5
Min
9.54 × 10
0.001
0.001
−7
Typ
2
±65
25
3
45
3
Typ
Max
750
750
750
250
0.27
0.5
1.0
Max
0.1
65.535
65.535
1.2
Rev. B | Page 7 of 104
Unit
MHz
MHz
MHz
V/μs
V
mV
kΩ
pF
ps
ps
MHz
V/μs
V
V
V
V
V
V
kΩ
pF
ns
ns
Unit
NPDP
Δf/f
sec
sec
REF
Test Conditions/Comments
Minimum limit imposed for jitter performance
Internally generated
This is the minimum voltage required across the pins to
ensure switching between logic states; the instantaneous
voltage on either pin must not exceed the supply rails
Minimum limit imposed for jitter performance
Test Conditions/Comments
NPDP = nominal phase detector period (NPDP = f
Programmable (lower bound subject to quality of SYSCLK)
Programmable in 1 ms increments
Programmable in 1 ms increments
AD9547
REF
/R)
1