AD9547/PCBZ Analog Devices Inc, AD9547/PCBZ Datasheet - Page 10

• Manufacturer Part Number: AD9547/PCBZ
• Description: Clock Generator/Synchronizer Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9547/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9547
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9547
• Primary Attributes: 2 Differential or 4 Single Ended Inputs
• Secondary Attributes: CMOS, LVPECL & LVDS Compatible
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9547
TIME DURATION OF DIGITAL FUNCTIONS
Table 13.
Parameter
EEPROM-TO-REGISTER DOWNLOAD TIME
REGISTER-TO-EEPROM UPLOAD TIME
MINIMUM POWER-DOWN EXIT TIME
MAXIMUM TIME FROM ASSERTION OF THE RESET PIN
DIGITAL PLL
Table 14.
Parameter
PHASE FREQUENCY DETECTOR (PFD) INPUT
LOOP BANDWIDTH
PHASE MARGIN
REFERENCE INPUT (R) DIVISION FACTOR
INTEGER FEEDBACK (S) DIVISION FACTOR
FRACTIONAL FEEDBACK DIVIDE RATIO
1
2
3
DIGITAL PLL LOCK DETECTION
Table 15.
Parameter
PHASE LOCK DETECTOR
FREQUENCY LOCK DETECTOR
HOLDOVER SPECIFICATIONS
Table 16.
Parameter
FREQUENCY ACCURACY
f
f
f
PFD
S
REF
TO THE M0 TO M7 PINS ENTERING HIGH
IMPEDANCE STATE
FREQUENCY RANGE
Threshold Programming Range
Threshold Resolution
Threshold Programming Range
Threshold Resolution
is the sample rate of the output DAC.
is the frequency of the active reference; R is the frequency division factor determined by the R divider.
is the frequency at the input to the phase-frequency detector.
0.001
30
0
Min
Min
0.001
1
8
Min
0.001
0.001
Min
Rev. B | Page 10 of 104
Typ
<0.01
Typ
25
200
10.5
45
Typ
Typ
1
1
Max
10
1 × 10
89
2
2
0.999
Max
Max
65.5
16,700
Max
30
20
5
Unit
ms
ms
μs
ns
Unit
MHz
Hz
Degrees
Unit
ns
ps
ns
ps
Unit
ppm
Test Conditions/Comments
Using default EEPROM storage sequence
(see Register 0x0E10 to Register 0x0E3F)
Using default EEPROM storage sequence
(see Register 0x0E10 to Register 0x0E3F
Dependent on loop filter bandwidth
Test Conditions/Comments
Maximum f
Programmable design parameter;
maximum f
Programmable design parameter
1, 2, …1,073,741,824
8, 9, …1,048,576
Maximum value = 1022/1023
Test Conditions/Comments
Reference-to-feedback period difference
Test Conditions/Comments
Excludes frequency drift of SYSCLK source;
excludes frequency drift of input reference
prior to entering holdover
PFD
LOOP
= f
= f
S
/100
REF
/(20R)
1, 2
3