AD9547/PCBZ Analog Devices Inc, AD9547/PCBZ Datasheet - Page 13

• Manufacturer Part Number: AD9547/PCBZ
• Description: Clock Generator/Synchronizer Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9547/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9547
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9547
• Primary Attributes: 2 Differential or 4 Single Ended Inputs
• Secondary Attributes: CMOS, LVPECL & LVDS Compatible
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

JITTER GENERATION
Table 19.
Parameter
CONDITIONS: f
CONDITIONS: f
CONDITIONS: f
1
2
3
4
5
f
f
f
f
f
REF
DDS
LOOP
SYSCLK
S
f
Bandwidth: 100 Hz to 77 MHz
Bandwidth: 5 kHz to 20 MHz
Bandwidth: 20 kHz to 80 MHz
Bandwidth: 50 kHz to 80 MHz
Bandwidth: 4 MHz to 80 MHz
f
Bandwidth: 100 Hz to 77 MHz
Bandwidth: 5 kHz to 20 MHz
Bandwidth: 20 kHz to 80 MHz
Bandwidth: 50 kHz to 80 MHz
Bandwidth: 4 MHz to 80 MHz
f
Bandwidth: 100 Hz to 100 MHz
Bandwidth: 5 kHz to 20 MHz
Bandwidth: 20 kHz to 80 MHz
Bandwidth: 50 kHz to 80 MHz
Bandwidth: 4 MHz to 80 MHz
is the sample rate of the output DAC.
LOOP
LOOP
LOOP
is the frequency of the active reference.
is the output frequency of the DDS.
is the DPLL digital loop filter bandwidth.
is the frequency at the SYSCLKP and SYSCLKN pins.
= 100 Hz
= 1 kHz
= 1 kHz
REF
3
3
REF
REF
3
= 19.44 MHz
= 8 kHz
= 19.44 MHz
1
, f
DDS
1
, f
1
, f
= 155.52 MHz
DDS
DDS
= 155.52 MHz
= 311.04 MHz
2
,
2
,
2
,
Min
Rev. B | Page 13 of 104
Typ
0.71
0.34
0.43
0.43
0.31
1.05
0.34
0.43
0.43
0.32
0.67
0.31
0.33
0.33
0.16
Max
Unit
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
Test Conditions/Comments
f
Q-divider = 1; default SYSCLK PLL charge
pump current; results valid for LVPECL,
LVDS, and CMOS output logic types
Random jitter
Random jitter
Random jitter
Random jitter
Random jitter
f
Q-divider = 1; default SYSCLK PLL charge
pump current; results valid for LVPECL,
LVDS, and CMOS output logic types
Random jitter
Random jitter
Random jitter
Random jitter
Random jitter
f
Q-divider = 1; default SYSCLK PLL charge
pump current; results valid for LVPECL,
LVDS, and CMOS output logic types
Random jitter
Random jitter
Random jitter
Random jitter
Random jitter
SYSCLK
SYSCLK
SYSCLK
= 50 MHz
= 50 MHz
= 50 MHz
4
4
4
crystal; f
crystal; f
crystal; f
S
S
S
= 1 GHz
= 1 GHz
= 1 GHz
AD9547
5
5
5
;
;
;