AD9547/PCBZ Analog Devices Inc, AD9547/PCBZ Datasheet - Page 44

• Manufacturer Part Number: AD9547/PCBZ
• Description: Clock Generator/Synchronizer Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9547/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9547
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9547
• Primary Attributes: 2 Differential or 4 Single Ended Inputs
• Secondary Attributes: CMOS, LVPECL & LVDS Compatible
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9547
STATUS AND CONTROL
MULTIFUNCTION PINS (M0 TO M7)
The AD9547 has eight digital CMOS I/O pins (M0 to M7) that are
configurable for a variety of uses. The function of these pins is
programmable via the register map. Each pin can control or moni-
tor an assortment of internal functions, based on the contents of
Register 0x0200 to Register 0x0207. To monitor an internal
function with a multifunction pin, write a Logic 1 to the MSB
of the register associated with the desired multifunction pin. The
value of the seven LSBs of the register defines the control function,
as shown in Table 24.
Table 24. Multifunction Pin Output Functions (D7 = 1)
D[6:0]
Value
0
1
2
3
4
5
6
7
8
9
10
11
12 to 15
16
17
18
19
20
21
22
23
24
25
26
27 to 31
32
33
34
35
36 to 47
48
49
50
51
52 to 63
64
65
66
67
68 to 79
Output Function
Static Logic 0
Static Logic 1
System clock divided by 32
Watchdog timer output
EEPROM upload in progress
EEPROM download in progress
EEPROM fault detected
SYSCLK PLL lock detected
SYSCLK PLL calibration in progress
Unused
Unused
SYSCLK PLL stable
Unused
DPLL free running
DPLL active
DPLL in holdover
DPLL in reference switchover
Active reference: phase master
DPLL phase locked
DPLL frequency locked
DPLL phase slew limited
DPLL frequency clamped
Tuning word history available
Tuning word history updated
Unused
Reference A fault
Reference AA fault
Reference B fault
Reference BB fault
Unused
Reference A valid
Reference AA valid
Reference B valid
Reference BB valid
Unused
Reference A active reference
Reference AA active reference
Reference B active reference
Reference BB active reference
Unused
Source Proxy
Register 0x0D00, Bit 0
Register 0x0D00, Bit 1
Register 0x0D00, Bit 2
Register 0x0D01, Bit 0
Register 0x0D01, Bit 1
Unused
Unused
Register 0x0D01, Bit 4
Unused
Register 0x0D0A, Bit 0
Register 0x0D0A, Bit 1
Register 0x0D0A, Bit 2
Register 0x0D0A, Bit 3
Register 0x0D0A, Bit 6
Register 0x0D0A, Bit 4
Register 0x0D0A, Bit 5
Register 0x0D0A, Bit 7
Register 0x0D0B, Bit 7
Register 0x0D0B, Bit 6
Register 0x0D05, Bit 4
Unused
Register 0x0D0C, Bit 2
Register 0x0D0D, Bit 2
Register 0x0D0E, Bit 2
Register 0x0D0F, Bit 2
Unused
Register 0x0D0C, Bit 3
Register 0x0D0D, Bit 3
Register 0x0D0E, Bit 3
Register 0x0D0F, Bit 3
Unused
Register 0x0D0B,
Bits[1:0]
Register 0x0D0B,
Bits[1:0}
Register 0x0D0B,
Bits[1:0]
Register 0x0D0B,
Bits[1:0]
Unused
Rev. B | Page 44 of 104
D[6:0]
Value
80
81 to
127
To control an internal function with a multifunction pin, write a
Logic 0 to the most significant bit of the register associated with
the desired multifunction pin. The monitored function depends
on the value of the seven least significant bits of the register, as
shown in Table 25. Note that the default setting is M0 through
M7 configured as inputs and the input function set to unused
(the first entry in Table 25).
Table 25. Multifunction Pin Input Functions (D7 = 0)
D[6:0]
Value
0
1
2
3
4
5
6 to 15
16
17
18
19
20
21 to 31
32
33
34
35
36 to 47
48
49
50
51
52 to 63
64
65
66, 67
68
69
70 to 127
If more than one multifunction pin operates on the same control
signal, then internal priority logic ensures that only one multi-
function pin serves as the signal source. The selected pin is the
one with the lowest numeric suffix. For example, if both M3
and M7 operate on the same control signal, M3 is used as the
signal source and the redundant pin is ignored.
Output Function
Clock distribution sync pulse
Unused
Input Function
Unused (default)
I/O update
Full power-down
Watchdog reset
IRQ reset
Tuning word history reset
Unused
Holdover
Free run
Reset incremental phase
offset
Increment incremental phase
offset
Decrement incremental
phase offset
Unused
Override Reference Monitor A
Override Reference Monitor AA
Override Reference Monitor B
Override Reference Monitor BB
Unused
Force Validation Timeout A
Force Validation Timeout AA
Force Validation Timeout B
Force Validation Timeout BB
Unused
Enable OUT0
Enable OUT1
Unused
Enable OUT0, OUT1
Sync clock distribution
outputs
Unused
Register 0x0A00, Bit 0
Register 0x0401, Bit 0
Register 0x0401, Bit 1
Destination Proxy
Unused
Register 0x0005, Bit 0
Register 0x0A03, Bit 0
Register 0x0A03, Bit 1
Register 0x0A03, Bit 2
Unused
Register 0x0A01, Bit 6
Register 0x0A01, Bit 5
Register 0x0A0C, Bit 2
Register 0x0A0C, Bit 0
Register 0x0A0C, Bit 1
Unused
Register 0x0A0F, Bit 0
Register 0x0A0F, Bit 1
Register 0x0A0F, Bit 2
Register 0x0A0F, Bit 3
Unused
Register 0x0A0E, Bit 0
Register 0x0A0E, Bit 1
Register 0x0A0E, Bit 2
Register 0x0A0E, Bit 3
Unused
Unused
Register 0x0401, Bits[1:0]
Register 0x0A02, Bit 1
Unused
Source Proxy
Register 0x0D03, Bit 3