AD9547/PCBZ Analog Devices Inc, AD9547/PCBZ Datasheet - Page 33

• Manufacturer Part Number: AD9547/PCBZ
• Description: Clock Generator/Synchronizer Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9547/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9547
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9547
• Primary Attributes: 2 Differential or 4 Single Ended Inputs
• Secondary Attributes: CMOS, LVPECL & LVDS Compatible
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Closed-Loop Phase Offset
The all-digital nature of the TDC/PFD provides for numerical
control of the phase offset between the reference and feedback
edges. This allows the user to adjust the relative timing of the
distribution output edges relative to the reference input edges by
programming the fixed phase lock offset bits (Address 0x030F to
Address 0x0313). The 40-bit word is a signed (twos complement)
number that represents units of picoseconds (ps).
In addition, the user can adjust the closed-loop phase offset (posi-
tive or negative) in incremental fashion. To do so, program the
desired step size in the incremental phase lock offset step size
bits (Address 0x0314 and Address 0x0315). This is an unsigned
number that represents units of picoseconds (ps). The program-
med step size is added to the current closed-loop phase offset each
time the user writes a Logic 1 to the increment phase offset bit
(Register 0x0A0C, Bit 0). Conversely, the programmed step size
is subtracted from the current closed-loop phase offset each time
the user writes a Logic 1 to the decrement phase offset bit
(Register 0x0A0C, Bit 1). The serial I/O port control logic clears
both of these bits automatically. The user can remove the incre-
mentally accumulated phase by writing a Logic 1 to the reset
incremental phase offset bit (Register 0x0A0C, Bit 2), which is
also cleared automatically. Alternatively, rather than using the
serial I/O port, the multifunction pins can be set up to perform
the increment, decrement, and clear functions.
Note that the incremental phase offset is completely independent of
the offset programmed into the fixed phase lock offset register.
However, if the phase slew limiter is active (see the Hitless
Reference Switching (Phase Slew Control) section), any instan-
taneous change in closed-loop phase offset (fixed or incremental)
is subject to possible slew limitation by the action of the phase
slew limiter.
Programmable Digital Loop Filter
The AD9547 loop filter is a third-order digital IIR filter that is
analogous to the third-order analog loop shown in Figure 37.
The filter requires four coefficients, as shown in Figure 38. The
AD9547 evaluation board software automatically generates the
required loop filter coefficient values based on user design cri-
teria. The Calculating the Digital Filter Coefficients section
contains the design equations for calculating the loop filter
coefficients manually.
Each coefficient has a fractional component representing a value
from 0 up to, but not including, unity. Each also has an expo-
nential component representing a power of 2 with a negative
exponent. That is, the user enters a positive number (x) that the
hardware interprets as a negative exponent of two (2
Figure 37. Third-Order Analog Loop Filter
C
1
R
C
2
R
2
3
C
3
−x
).
Rev. B | Page 33 of 104
Thus, the β, γ, and δ coefficients always represent values less than
unity. The α coefficient, however, has two additional exponential
components, but the hardware interprets these as a positive
exponent of two (that is, 2
on values that are greater than unity. To provide sufficient dynamic
range, the positive exponent appears as two separate terms.
DPLL Phase Lock Detector
The DPLL contains an all-digital phase lock detector. The user
controls the threshold sensitivity and hysteresis of the phase
lock detector via the profile registers.
The phase lock detector behaves in a manner that is analogous
to water in a tub (see Figure 39). The total capacity of the tub is
4096 units with −2048 denoting empty, 0 denoting the 50% point,
and +2048 denoting full. The tub also has a safeguard to prevent
overflow. Furthermore, the tub has a low water mark at −1024
and a high water mark at +1024. To change the water level, the
user adds water with a fill bucket or removes water with a drain
bucket. The user specifies the size of the fill and drain buckets via
the 8-bit fill rate and drain rate values in the profile registers.
The phase lock detector uses the water level in the tub to determine
the lock and unlock conditions. When the water level is below
the low water mark (−1024), the detector indicates an unlock
con-dition. Conversely, when the water level is above the high
water mark (+1024), the detector indicates a lock condition.
When the water level is between the marks, the detector holds its
last condition. This concept appears graphically in Figure 39, with
an overlay of an example of the instantaneous water level (vertical)
vs. time (horizontal) and the resulting lock/unlock states.
2048
FRACTIONAL
1024
IN
(16-BIT)
–1024
(6-BIT)
(3-BIT)
(4-BIT)
0
–2048
1/2
51
2
2
x
x
x
PREVIOUS
STATE
α
α
α
α
α
0
1
2
3
Figure 38. Third-Order Digital IIR Loop Filter
Figure 39. Phase Lock Detector Diagram
FRACTIONAL
FILL
RATE
(17-BIT)
(6-BIT)
1/2
DRAIN
RATE
x
(THIRD-ORDER IIR)
x
LOCKED
). This allows the α coefficient to take
LOOP FILTER
β
β
β
0
1
0
1
FRACTIONAL
(17-BIT)
1/2
(6-BIT)
x
UNLOCKED
UNLOCK LEVEL
σ
σ
σ
0
1
LOCK LEVEL
48
AD9547
FRACTIONAL
(15-BIT)
1/2
(5-BIT)
x
OUT