AD9547/PCBZ Analog Devices Inc, AD9547/PCBZ Datasheet - Page 16

• Manufacturer Part Number: AD9547/PCBZ
• Description: Clock Generator/Synchronizer Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9547/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9547
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9547
• Primary Attributes: 2 Differential or 4 Single Ended Inputs
• Secondary Attributes: CMOS, LVPECL & LVDS Compatible
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9547
Pin No.
20
21
23
24
25, 31
26
27
28, 32
29
30
33
34
35
36, 39
37
38
40, 41
42
43, 49
44
45
46, 50
Input/
Output
I
I
I
O
I
O
O
I
O
O
I
I
O
I
I
I
I
I
I
I
I
I
Power
Power
Power
Power
Power
Power
Pin Type
Differential
input
Differential
input
Current set
resistor
Power
LVPECL,
LVDS, or
CMOS
LVPECL,
LVDS, or
CMOS
Power
LVPECL,
LVDS, or
CMOS
LVPECL,
LVDS, or
CMOS
Differential
input
Differential
input
Differential
input
Differential
input
Mnemonic
CLKINN
CLKINP
AVDD
OUT_RSET
AVDD3
OUT0P
OUT0N
AVDD
OUT1P
OUT1N
AVDD3
SYSCLK_VREG
SYSCLK_LF
AVDD
SYSCLKN
SYSCLKP
TDC_VRB,
TDC_VRT
AVDD
AVDD3
REFA
REFAA
AVDD
Rev. B | Page 16 of 104
Description
Clock Distribution Input. In standard operating mode, this pin is connected to
the filtered DACOUTN output. This internally biased input is typically ac-coupled,
and, when configured as such, can accept any differential signal with a single-
ended swing of at least 400 mV.
Clock Distribution Input. In standard operating mode, this pin is connected to
the filtered DACOUTP output.
1.8 V Analog (Input Receiver) Power Supply.
Connect an optional 3.12 kΩ resistor from this pin to ground (see the Output
Current Control with an External Resistor section).
Analog Supply for Output Driver. These pins are normally 3.3 V but can be
1.8 V. Pin 25 powers OUT0. Pin 31 powers OUT1. Apply power to these pins
even if the corresponding outputs (OUT0P/OUT0N, OUT1P/OUT1N) are not
used. See the Power Supply Partitions section.
Output 0. This output can be configured as LVPECL, LVDS, or single-ended
CMOS. LVPECL and LVDS operation require a 3.3 V output driver power
supply. CMOS operation can be either 1.8 V or 3.3 V, depending on the output
driver power supply.
Complementary Output 0. This output can be configured as LVPECL, LVDS, or
single-ended CMOS.
1.8 V Analog (Output Divider) Power Supply.
Output 1. This output can be configured as LVPECL, LVDS, or single-ended
CMOS. LVPECL and LVDS operation require a 3.3 V output driver power
supply. CMOS operation can be either 1.8 V or 3.3 V, depending on the output
driver power supply.
Complementary Output 1. This output can be configured as LVPECL, LVDS, or
single-ended CMOS.
3.3 V Analog (System Clock) Power Supply.
System Clock Loop Filter Voltage Regulator. Connect a 0.1 μF capacitor from
this pin to ground. This pin is also the ac ground reference for the integrated
external loop filter of the SYSCLK PLL multiplier (see the SYSCLK PLL Multiplier
section).
System Clock Multiplier Loop Filter. When using the frequency multiplier to
drive the system clock, an external loop filter can be attached to this pin.
1.8 V Analog (System Clock) Power Supply.
Complementary System Clock Input. Complementary signal to SYSCLKP.
SYSCLKN contains internal dc biasing and should be ac-coupled with a 0.01 μF
capacitor, except when using a crystal. When using a crystal, connect it across
SYSCLKP and SYSCLKN.
System Clock Input. SYSCLKP contains internal dc biasing and should be ac-
coupled with a 0.01 μF capacitor, except when using a crystal. When using a
crystal, connect it directly across SYSCLKP and SYSCLKN. Single-ended 1.8 V
CMOS is also an option but can introduce a spur if the duty cycle is not 50%.
When using SYSCLKP as a single-ended input, connect a 0.01 μF capacitor
from SYSCLKN to ground.
Use capacitive decoupling on these pins (see Figure 36).
1.8 V Analog (Time-to-Digital Converter) Power Supply.
3.3 V Analog (Reference Input) Power Supply.
Reference A Input. This internally biased input is typically ac-coupled and,
when configured as such, can accept any differential signal with a single-
ended swing of up to 3.3 V. If dc-coupled, input can be LVPECL, CMOS, or LVDS.
Complementary Reference A Input. Complementary signal to the input pro-
vided on Pin 44. The user can configure this pin as a separate single-ended input.
1.8 V Analog (Reference Input) Power Supply.