AD9547/PCBZ Analog Devices Inc, AD9547/PCBZ Datasheet - Page 41

• Manufacturer Part Number: AD9547/PCBZ
• Description: Clock Generator/Synchronizer Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9547/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9547
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9547
• Primary Attributes: 2 Differential or 4 Single Ended Inputs
• Secondary Attributes: CMOS, LVPECL & LVDS Compatible
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Output Mode
The user has independent control of the operating mode of each of
the two output channels via the distribution channel modes register
(Address 0x0404 and Address 0x0405). The operating mode
control includes
•
•
•
The three LSBs of both distribution channel mode registers com-
prise the mode bits. The mode value selects the desired logic
family and pin functionality of an output channel, as listed in
Table 23.
Table 23. Output Channel Logic Family and Pin Functionality
Mode Bits [2:0]
000
001
010
011
100
101
110
111
Regardless of the selected logic family, each is capable of dc
operation. However, the upper frequency is limited by the load
conditions, drive strength, and impedance matching inherent in
each logic family. Practical limitations set the maximum CMOS
frequency to approximately 250 MHz, whereas LVPECL and
LVDS are capable of 725 MHz.
In addition to the three mode bits, both distribution channel
mode registers include the following control bits:
•
•
•
The polarity invert bit enables the user to choose between normal
polarity and inverted polarity. Normal polarity is the default
state. Inverted polarity reverses the representation of Logic 0
and Logic 1 regardless of the logic family.
The CMOS phase invert bit applies only when the mode bits select
the CMOS logic family. In CMOS mode, both output pins of the
channel have a dedicated CMOS driver. By default, both drivers
deliver identical signals. However, setting the CMOS phase invert
bit causes the signal on an OUTxN pin to be the opposite of the
signal appearing on the OUTxP pin.
The drive strength bit allows the user to control whether the
output uses weak (0) or strong (1) drive capability (applies to
CMOS and LVDS but not LVPECL). For the CMOS family, the
strong setting implies normal CMOS drive capability, whereas
the weak setting implies low capacitive loading and allows for
reduced EMI. For the LVDS family, the weak setting provides
3.5 mA drive current for standard LVDS operation, whereas the
Logic family and pin functionality
Output drive strength
Output polarity
Polarity invert
CMOS phase invert
Drive strength
Logic Family and Pin Functionality
CMOS (both pins)
CMOS (positive pin), tristate (negative pin)
Tristate (positive pin), CMOS (negative pin)
Tristate (both pins)
LVDS
LVPECL
Unused
Unused
Rev. B | Page 41 of 104
strong setting provides 7 mA for double terminated or double
voltage LVDS operation. Note that 3.5 mA and 7 mA are the
nominal drive current values when using the internal current
setting resistor.
Output Current Control with an External Resistor
By default, the output drivers have an internal current setting
resistor (3.12 kΩ nominal) that establishes the nominal drive
current for the LVDS and LVPECL operating modes. Instead of
using the internal resistor, the user can elect to set the external
distribution resistor bit (Register 0x0400, Bit 5) and connect an
external resistor to the OUT_RSET pin. Note that this feature
supports an external resistor value of 3.12 kΩ only, allowing for
tighter control of the output current than is possible by using
the internal current setting resistor. However, if the user elects
to use a nonstandard external resistance, the following equations
provide the output drive current as a function of the external
resistance (R):
The numeric subscript associated with the LVDS output cur-
rent corresponds to the logic state of the drive strength bit in the
distribution channel modes registers (Address 0x0404, Bit 3 and
Address 0x0405, Bit 3). For R = 3.12 kΩ, the equations yield
I
the device maintains a constant 1.238 V (nominal) across the
external resistor.
Clock Distribution Synchronization
A block diagram of the distribution synchronization functionality
appears in Figure 46. The synchronization sequence begins with
the primary synchronization signal, which ultimately results in
delivery of a synchronization strobe to the clock distribution logic.
As indicated, the primary synchronization signal originates
from the following four possible sources:
•
•
•
•
All four sources of the primary synchronization signal are logic
OR’ d , so any one of them can synchronize the clock distribution
output at any time. When using the multifunction pins, the syn-
chronization event is the falling edge of the selected signal. When
using the sync distribution bit, the user first sets then clears the bit.
LVDS0
Direct synchronization source via the sync distribution bit
(Register 0x0A02, Bit 1)
Automatic synchronization source based on frequency or
phase lock detection, as controlled via the automatic synchro-
nization register (Address 0x0403)
Multifunction pin synchronization source via one of the
multifunction pins (M0 to M7)
EEPROM synchronization source via the EEPROM
I
I
I
= 3.5 mA, I
LVDS
LVDS
LVPECL
1
0
=
=
=
10
21
24
.
.
R
8325
665
R
R
.
LVDS1
76
= 7.0 mA, and I
LVPECL
= 8.0 mA. Note that
AD9547