PIC24FJ64GB004-I/ML Microchip Technology, PIC24FJ64GB004-I/ML Datasheet - Page 54

• Manufacturer Part Number: PIC24FJ64GB004-I/ML
• Description: IC, 16BIT MCU, PIC24F, 32MHZ, QFN-44
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FJ64GB004-I/ML

• Controller Family/series: PIC24
• Ram Memory Size: 8KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Interface: I2C, LIN, SPI, UART, USB
• No. Of Pwm Channels: 5
• Core Size: 16 Bit
• Program Memory Size: 64 KB
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Embedded Interface Type: I2C, LIN, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC24FJ64GB004 FAMILY
5.2
The PIC24F Flash program memory array is organized
into rows of 64 instructions or 192 bytes. RTSP allows
the user to erase blocks of eight rows (512 instructions)
at a time and to program one row at a time. It is also
possible to program single words.
The 8-row erase blocks and single row write blocks are
edge-aligned, from the beginning of program memory, on
boundaries of 1536 bytes and 192 bytes, respectively.
When data is written to program memory using TBLWT
instructions, the data is not written directly to memory.
Instead, data written using table writes is stored in
holding latches until the programming sequence is
executed.
Any number of TBLWT instructions can be executed
and a write will be successfully performed. However,
64 TBLWT instructions are required to write the full row
of memory.
To ensure that no data is corrupted during a write, any
unused addresses should be programmed with
FFFFFFh. This is because the holding latches reset to
an unknown state, so if the addresses are left in the
Reset state, they may overwrite the locations on rows
which were not rewritten.
The basic sequence for RTSP programming is to set up
a Table Pointer, then do a series of TBLWT instructions
to load the buffers. Programming is performed by
setting the control bits in the NVMCON register.
Data can be loaded in any order and the holding regis-
ters can be written to multiple times before performing
a write operation. Subsequent writes, however, will
wipe out any previous writes.
All of the table write operations are single-word writes
(2 instruction cycles), because only the buffers are writ-
ten. A programming cycle is required for programming
each row.
DS39940C-page 52
Note:
RTSP Operation
Writing to a location multiple times without
erasing is not recommended.
Preliminary
5.3
The PIC24F family supports JTAG programming and
boundary scan. Boundary scan can improve the manu-
facturing process by verifying pin to PCB connectivity.
Programming can be performed with industry standard
JTAG programmers supporting Serial Vector Format
(SVF).
5.4
Enhanced In-Circuit Serial Programming uses an
on-board bootloader, known as the program executive,
to manage the programming process. Using an SPI
data frame format, the program executive can erase,
program and verify program memory. For more
information on Enhanced ICSP, see the device
programming specification.
5.5
There are two SFRs used to read and write the
program Flash memory: NVMCON and NVMKEY.
The NVMCON register (Register 5-1) controls which
blocks are to be erased, which memory type is to be
programmed and when the programming cycle starts.
NVMKEY is a write-only register that is used for write
protection. To start a programming or erase sequence,
the user must consecutively write 55h and AAh to the
NVMKEY register. Refer to Section 5.6 “Programming
Operations” for further details.
5.6
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode. During a programming or erase operation, the
processor stalls (waits) until the operation is finished.
Setting the WR bit (NVMCON<15>) starts the
operation and the WR bit is automatically cleared when
the operation is finished.
JTAG Operation
Enhanced In-Circuit Serial
Programming
Control Registers
Programming Operations
© 2009 Microchip Technology Inc.