PIC24FJ64GB004-I/ML Microchip Technology, PIC24FJ64GB004-I/ML Datasheet - Page 203

• Manufacturer Part Number: PIC24FJ64GB004-I/ML
• Description: IC, 16BIT MCU, PIC24F, 32MHZ, QFN-44
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FJ64GB004-I/ML

• Controller Family/series: PIC24
• Ram Memory Size: 8KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Interface: I2C, LIN, SPI, UART, USB
• No. Of Pwm Channels: 5
• Core Size: 16 Bit
• Program Memory Size: 64 KB
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Embedded Interface Type: I2C, LIN, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

REGISTER 18-2:
© 2009 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13-12
bit 11
bit 10
bit 9-0
Note 1:
UOWN
R/W-x
R/W-x
BC7
This bit is ignored unless DTSEN = 1.
UOWN: USB Own bit
0 = The microcontroller core owns the BD and its corresponding buffer. The USB module ignores all
DTS: Data Toggle Packet bit
1 = Data 1 packet
0 = Data 0 packet
Reserved Function: Maintain as ‘0’
DTSEN: Data Toggle Synchronization Enable bit
1 = Data toggle synchronization is enabled; data packets with incorrect sync value will be ignored
0 = No data toggle synchronization is performed
BSTALL: Buffer Stall Enable bit
1 = Buffer STALL enabled; STALL handshake issued if a token is received that would use the BD in
0 = Buffer STALL disabled
BC<9:0>: Byte Count bits
This represents the number of bytes to be transmitted or the maximum number of bytes to be received
during a transfer. Upon completion, the byte count is updated by the USB module with the actual
number of bytes transmitted or received.
DTS
R/W-x
R/W-x
BC6
other fields in the BD.
the given location (UOWN bit remains set, BD value is unchanged); corresponding EPSTALL bit
will get set on any STALL handshake
BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER PROTOTYPE, CPU
MODE (BD0STAT THROUGH BD63STAT)
(1)
W = Writable bit
‘1’ = Bit is set
R/W-x
R/W-x
BC5
0
(1)
R/W-x
R/W-x
BC4
PIC24FJ64GB004 FAMILY
Preliminary
0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
DTSEN
R/W-x
R/W-x
BC3
BSTALL
R/W-x
R/W-x
BC2
x = Bit is unknown
R/W-x
R/W-x
BC9
BC1
DS39940C-page 201
R/W-x
R/W-x
BC8
BC0
bit 8
bit 0