PIC24FJ64GB004-I/ML Microchip Technology, PIC24FJ64GB004-I/ML Datasheet - Page 267

• Manufacturer Part Number: PIC24FJ64GB004-I/ML
• Description: IC, 16BIT MCU, PIC24F, 32MHZ, QFN-44
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FJ64GB004-I/ML

• Controller Family/series: PIC24
• Ram Memory Size: 8KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Interface: I2C, LIN, SPI, UART, USB
• No. Of Pwm Channels: 5
• Core Size: 16 Bit
• Program Memory Size: 64 KB
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Embedded Interface Type: I2C, LIN, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

23.0
The triple comparator module provides three dual input
comparators. The inputs to the comparator can be con-
figured to use any one of four external analog inputs, as
well as voltage reference inputs from the voltage
reference generator and band gap reference.
FIGURE 23-1:
© 2009 Microchip Technology Inc.
Note:
C
C
C
CV
C
CV
CCH<1:0>
CREF
X
X
X
X
INB
INC
IND
INA
TRIPLE COMPARATOR
MODULE
REF
REF
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
associated “PIC24F Family Reference
Manual”,
Module” (DS39710).
-
+
TRIPLE COMPARATOR MODULE BLOCK DIAGRAM
Section
Select
Logic
Input
19.
V
V
V
V
V
V
IN
IN
“Comparator
IN
IN
IN
IN
-
+
-
+
-
+
C1
C2
C3
PIC24FJ64GB004 FAMILY
Preliminary
CPOL
EVPOL<1:0>
EVPOL<1:0>
EVPOL<1:0>
CPOL
CPOL
The comparator outputs may be directly connected to
the CxOUT pins. When the respective COE equals ‘1’,
the I/O pad logic makes the unsynchronized output of
the comparator available on the pin.
A simplified block diagram of the module in shown in
Figure 23-1. Diagrams of the possible individual
comparator configurations are shown in Figure 23-2.
Each comparator has its own control register,
CMxCON (Register 23-1), for enabling and configuring
its operation. The output and event status of all three
comparators are provided in the CMSTAT register
(Register 23-2).
Trigger/Interrupt
Trigger/Interrupt
Trigger/Interrupt
Logic
Logic
Logic
COE
COE
COE
CEVT
CEVT
COUT
CEVT
COUT
COUT
DS39940C-page 265
C1OUT
C2OUT
C3OUT
Pin
Pin
Pin