PIC24FJ64GB004-I/ML Microchip Technology, PIC24FJ64GB004-I/ML Datasheet - Page 263

• Manufacturer Part Number: PIC24FJ64GB004-I/ML
• Description: IC, 16BIT MCU, PIC24F, 32MHZ, QFN-44
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FJ64GB004-I/ML

• Controller Family/series: PIC24
• Ram Memory Size: 8KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Interface: I2C, LIN, SPI, UART, USB
• No. Of Pwm Channels: 5
• Core Size: 16 Bit
• Program Memory Size: 64 KB
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Embedded Interface Type: I2C, LIN, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

REGISTER 22-5:
© 2009 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12-0
Note 1:
PCFG15
R/W-0
PCFG7
R/W-0
(1)
Analog channels, AN6, AN7, AN8 and AN12, are unavailable on 28-pin devices; leave these corresponding
bits set.
PCFG15: A/D Input Band Gap Reference Enable bit
1 = Internal band gap (V
0 = Internal band gap reference channel enabled
PCFG14: A/D Input Half Band Gap Reference Enable bit
1 = Internal half band gap (V
0 = Internal half band gap reference channel enabled
PCFG13: A/D Input Voltage Regulator Output Reference Enable bit
1 = Internal voltage regulator output (V
0 = Internal voltage regulator output reference channel enabled
PCFG<12:0>: Analog Input Pin Configuration Control bits
1 = Pin for corresponding analog channel is configured in Digital mode; I/O port read enabled
0 = Pin configured in Analog mode; I/O port read disabled, A/D samples pin voltage
PCFG14
R/W-0
PCFG6
R/W-0
AD1PCFG: A/D PORT CONFIGURATION REGISTER
(1)
W = Writable bit
‘1’ = Bit is set
PCFG13
PCFG5
R/W-0
R/W-0
BG
) reference channel disabled
BG
R/W-0
PCFG12
/2) reference channel disabled
PCFG4
R/W-0
PIC24FJ64GB004 FAMILY
Preliminary
(1)
DDCORE
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PCFG11
PCFG3
) reference channel disabled
R/W-0
R/W-0
(1)
PCFG10
PCFG2
R/W-0
R/W-0
x = Bit is unknown
PCFG9
PCFG1
R/W-0
R/W-0
DS39940C-page 261
R/W-0
PCFG0
PCFG8
R/W-0
(1)
bit 8
bit 0