PIC24FJ64GB004-I/ML Microchip Technology, PIC24FJ64GB004-I/ML Datasheet - Page 164

• Manufacturer Part Number: PIC24FJ64GB004-I/ML
• Description: IC, 16BIT MCU, PIC24F, 32MHZ, QFN-44
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FJ64GB004-I/ML

• Controller Family/series: PIC24
• Ram Memory Size: 8KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Interface: I2C, LIN, SPI, UART, USB
• No. Of Pwm Channels: 5
• Core Size: 16 Bit
• Program Memory Size: 64 KB
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Embedded Interface Type: I2C, LIN, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC24FJ64GB004 FAMILY
14.4
The DCB bits (OCxCON2<10:9>) provide for resolution
better than one instruction cycle. When used, they
delay the falling edge generated by a match event by a
portion of an instruction cycle.
For example, setting DCB<1:0> = 10 causes the falling
edge to occur halfway through the instruction cycle in
which the match event occurs, instead of at the
beginning.
OCM<2:0> = 001. When operating the module in PWM
mode (OCM<2:0> = 110 or 111), the DCB bits will be
double-buffered.
TABLE 14-1:
TABLE 14-2:
DS39940C-page 162
Timer Prescaler Ratio
Period Register Value
Resolution (bits)
Note 1:
Timer Prescaler Ratio
Period Register Value
Resolution (bits)
Note 1:
PWM Frequency
PWM Frequency
Subcycle Resolution
Based on F
Based on F
These
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 4 MIPS (F
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 16 MIPS (F
bits
CY
CY
= F
= F
cannot
OSC
OSC
30.5 Hz
FFFFh
/2, Doze mode and PLL are disabled.
FFFFh
/2, Doze mode and PLL are disabled.
7.6 Hz
16
16
8
8
be
used
244 Hz
FFFFh
FFFFh
61 Hz
16
16
1
1
when
Preliminary
122 Hz
488 Hz
7FFFh
7FFFh
15
15
1
1
The DCB bits are intended for use with a clock source
identical to the system clock. When a timer with
enabled prescaler is used, the falling edge delay
caused by the DCB bits will be referenced to the
system clock period rather than the timer’s period.
3.9 kHz
977 Hz
0FFFh
0FFFh
12
12
1
1
15.6 kHz
3.9 kHz
03FFh
03FFh
10
10
1
1
© 2009 Microchip Technology Inc.
31.3 kHz
125 kHz
007Fh
007Fh
CY
1
7
CY
1
7
= 4 MHz)
= 16 MHz)
125 kHz
500 kHz
001Fh
001Fh
(1)
1
5
1
5
(1)