PIC24FJ64GB004-I/ML Microchip Technology, PIC24FJ64GB004-I/ML Datasheet - Page 121

• Manufacturer Part Number: PIC24FJ64GB004-I/ML
• Description: IC, 16BIT MCU, PIC24F, 32MHZ, QFN-44
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FJ64GB004-I/ML

• Controller Family/series: PIC24
• Ram Memory Size: 8KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Interface: I2C, LIN, SPI, UART, USB
• No. Of Pwm Channels: 5
• Core Size: 16 Bit
• Program Memory Size: 64 KB
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Embedded Interface Type: I2C, LIN, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

REGISTER 9-1:
© 2009 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
HC = Hardware Clearable bit
bit 15
bit 14-2
bit 1
bit 0
Note 1:
R/W-0, HC
DSEN
U-0
—
2:
3:
(1)
These bits are reset only in the case of a POR event outside of Deep Sleep mode.
Reset value is ‘0’ for initial power-on POR only and ‘1’ for Deep Sleep POR.
This is a status bit only; a DSBOR event will NOT cause a wake-up from Deep Sleep.
DSEN: Deep Sleep Enable bit
1 = Device enters Deep Sleep when PWRSAV #0 is executed in the next instruction
0 = Device enters normal Sleep when PWRSAV #0 is executed
Unimplemented: Read as ‘0’
DSBOR: Deep Sleep BOR Event Status bit
1 = The DSBOR was active and a BOR event was detected during Deep Sleep
0 = The DSBOR was disabled or was active and did not detect a BOR event during Deep Sleep
RELEASE: I/O Pin State Deep Sleep Release bit
1 = I/O pins and SOSC maintain their states following exit from Deep Sleep, regardless of their LAT
0 = I/O pins and SOSC are released from their Deep Sleep states. The pin state is controlled by the
and TRIS configuration
LAT and TRIS configurations, and the SOSCEN bit.
U-0
U-0
—
—
DSCON: DEEP SLEEP CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
HS = Hardware Settable bit
U-0
U-0
—
—
(1)
PIC24FJ64GB004 FAMILY
Preliminary
U-0
U-0
—
—
(1,2,3)
C = Clearable bit
‘0’ = Bit is cleared
HCS = Hardware Clearable/Settable bit
U-0
U-0
—
—
(1,2)
U-0
U-0
—
—
U = Unimplemented, read as ‘0’
x = Bit is unknown
DSBOR
R/W-0, HCS
U-0
—
(1,2,3)
DS39940C-page 119
RELEASE
R/C-0, HS
U-0
—
(1,2)
bit 8
bit 0