PIC24FJ64GB004-I/ML Microchip Technology, PIC24FJ64GB004-I/ML Datasheet - Page 125

• Manufacturer Part Number: PIC24FJ64GB004-I/ML
• Description: IC, 16BIT MCU, PIC24F, 32MHZ, QFN-44
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FJ64GB004-I/ML

• Controller Family/series: PIC24
• Ram Memory Size: 8KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Interface: I2C, LIN, SPI, UART, USB
• No. Of Pwm Channels: 5
• Core Size: 16 Bit
• Program Memory Size: 64 KB
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Embedded Interface Type: I2C, LIN, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

10.0
All of the device pins (except V
OSCI/CLKI) are shared between the peripherals and
the parallel I/O ports. All I/O input ports feature Schmitt
Trigger inputs for improved noise immunity.
10.1
A parallel I/O port that shares a pin with a peripheral is, in
general, subservient to the peripheral. The peripheral’s
output buffer data and control signals are provided to a
pair of multiplexers. The multiplexers select whether the
peripheral or the associated port has ownership of the
output data and control signals of the I/O pin. The logic
also prevents “loop through”, in which a port’s digital out-
put can drive the input of a peripheral that shares the
same pin. Figure 10-1 shows how ports are shared with
other peripherals and the associated I/O pin to which
they are connected.
FIGURE 10-1:
© 2009 Microchip Technology Inc.
Note:
I/O PORTS
Parallel I/O (PIO) Ports
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
“PIC24F
Section 12. “I/O Ports with Peripheral
Pin Select (PPS)” (DS39711).
Read TRIS
Data Bus
WR TRIS
WR LAT +
WR PORT
Read LAT
Read PORT
Family
BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE
Peripheral Input Data
Peripheral Module Enable
Peripheral Output Enable
Peripheral Output Data
Peripheral Module
PIO Module
Reference
TRIS Latch
DD
Data Latch
D
D
CK
CK
, V
SS
Q
Q
, MCLR and
Manual”,
PIC24FJ64GB004 FAMILY
Preliminary
Output Multiplexers
When a peripheral is enabled and the peripheral is
actively driving an associated pin, the use of the pin as
a general purpose output pin is disabled. The I/O pin
may be read, but the output driver for the parallel port
bit will be disabled. If a peripheral is enabled, but the
peripheral is not actively driving a pin, that pin may be
driven by a port.
All port pins have three registers directly associated
with their operation as digital I/Os. The Data Direction
register (TRIS) determines whether the pin is an input
or an output. If the data direction bit is a ‘1’, then the pin
is an input. All port pins are defined as inputs after a
Reset. Reads from the Output Latch register (LAT),
read the latch. Writes to the Output Latch register, write
the latch. Reads from the port (PORT), read the port
pins, while writes to the port pins, write the latch.
Any bit and its associated data and control registers
that are not valid for a particular device will be
disabled. That means the corresponding LAT and
TRIS registers, and the port pin will read as zeros.
When a pin is shared with another peripheral or func-
tion that is defined as an input only, it is regarded as a
dedicated port because there is no other competing
source of outputs.
1
0
1
0
Output Enable
Output Data
Input Data
I/O
I/O Pin
DS39940C-page 123