NANDO1GW3B2CN6 NUMONYX, NANDO1GW3B2CN6 Datasheet - Page 12

IC, FLASH, 1GB, 25µS, TSOP-48

NANDO1GW3B2CN6

Manufacturer Part Number
NANDO1GW3B2CN6
Description
IC, FLASH, 1GB, 25µS, TSOP-48
Manufacturer
NUMONYX
Datasheet

Specifications of NANDO1GW3B2CN6

Memory Type
FLASH
Memory Size
1GB
Access Time
25µS
Supply Voltage Range
2.7V TO 3.6V
Memory Case Style
TSOP
No. Of Pins
48
Operating Temperature Range
-40°C TO +85°C
Voltage, Vcc
3.3V
Memory Configuration
128M X 8
Rohs Compliant
Yes
Memory array organization
2
2.1
12/60
Memory array organization
The memory array is made up of NAND structures where 32 cells are connected in series.
The memory array is organized in blocks where each block contains 64 pages. The array is
split into two areas, the main area and the spare area. The main area of the array is used to
store data whereas the spare area is typically used to store error correction codes, software
flags or bad block identification.
In x8 devices the pages are split into a 2048-byte main area and a spare area of 64 bytes. In
the x16 devices the pages are split into a 1,024-word main area and a 32-word spare area.
Refer to
Bad blocks
The NAND flash 2112-byte/1056-word page devices may contain bad blocks, that is blocks
that contain one or more invalid bits whose reliability is not guaranteed. Additional bad
blocks may develop during the lifetime of the device.
The bad block Information is written prior to shipping (refer to
management
Table 4: Valid blocks
shown include both the bad blocks that are present when the device is shipped and the bad
blocks that could develop later on.
These blocks need to be managed using bad blocks management, block replacement or
error correction codes (refer to
Table 4.
Figure 5: Memory array
Density of device
Valid blocks
for more details).
2 Gbits
1 Gbit
shows the minimum number of valid blocks in each device. The values
Section 8: Software
organization.
2008
1004
Min
algorithms).
NAND01G-B2B, NAND02G-B2C
Section 8.1: Bad block
2048
1024
Max

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