NANDO1GW3B2CN6 NUMONYX, NANDO1GW3B2CN6 Datasheet
NANDO1GW3B2CN6
Specifications of NANDO1GW3B2CN6
Related parts for NANDO1GW3B2CN6
NANDO1GW3B2CN6 Summary of contents
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... ECOPACK packages Development tools – Error correction code models – Bad blocks management and wear leveling algorithms – Hardware simulation models Part number NAND01GR3B2B, NAND01GW3B2B , NAND01GR4B2B NAND01GW4B2B NAND02GR3B2C, NAND02GW3B2C NAND02GR4B2C, NAND02GW4B2C Rev 5 1-Gbit, 2-Gbit, (1) (1) 1/60 www.numonyx.com 1 ...
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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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NAND01G-B2B, NAND02G-B2C 6.2 Cache read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Contents 12 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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NAND01G-B2B, NAND02G-B2C List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of figures List of figures Figure 1. Logic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... All devices have the option of a unique identifier (serial number), which allows each device to be uniquely identified. The unique identifier options is subject to an NDA (non disclosure agreement) and so not described in the datasheet. For more details of this option contact your nearest Numonyx sales office. The devices are available in the following packages: TSOP48 ( mm) VFBGA63 (9 ...
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Description Table 2. Product description Reference Part number Density NAND01GR3B2B NAND01GW3B2B NAND01G 1Gbit -B2B NAND01GR4B2B NAND01GW4B2B NAND02GR3B2C NAND02GW3B2C NAND02G 2Gbits -B2C NAND02GR4B2C NAND02GW4B2C 1. x16 organization only available for MCP. Figure 1. Logic block diagram Address register/counter AL CL Command ...
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NAND01G-B2B, NAND02G-B2C Figure 2. Logic diagram 1. x16 organization only available for MCP. Table 3. Signal names Signal I/O8-15 Data input/outputs for x16 devices Data input/outputs, address inputs, or command inputs I/O0-7 for x8 and x16 devices AL Address Latch ...
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Description Figure 3. TSOP48 connections 1. Available only for NAND01GW3B2B and NAND02GW3B2C 8-bit devices. 10/ NAND01GW3B2B 37 NAND02GW3B2C ...
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NAND01G-B2B, NAND02G-B2C Figure 4. VFBGA63 connections (top view through package Available only for NAND01GR3B2B and NAND02GR3B2C 8-bit devices. ...
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Memory array organization 2 Memory array organization The memory array is made up of NAND structures where 32 cells are connected in series. The memory array is organized in blocks where each block contains 64 pages. The array is split ...
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NAND01G-B2B, NAND02G-B2C Figure 5. Memory array organization x8 DEVICES Block = 64 pages Page = 2112 bytes (2,048 + 64) Main area Block Page 2048 bytes Page buffer, 2112 bytes 2,048 bytes Block Page 8 bits 64 bytes 64 8 ...
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Signals description 3 Signals description See Figure 2: Logic connected to this device. 3.1 Inputs/outputs (I/O0-I/O7) Input/outputs are used to input the selected address, output the data during a read operation or input a command or data ...
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NAND01G-B2B, NAND02G-B2C 3.7 Write Enable (W) The Write Enable input, W, controls writing to the command interface, input address and data latches. Both addresses and data are latched on the rising edge of Write Enable. During power-up and power-down a ...
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Bus operations 4 Bus operations There are six standard bus operations that control the memory. Each of these is described in this section, see Typically, glitches of less than Chip Enable, Write Enable and Read Enable are ...
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NAND01G-B2B, NAND02G-B2C 4.5 Write Protect Write Protect bus operations are used to protect the memory against program or erase operations. When the Write Protect signal is Low the device will not accept program or erase operations and so the contents ...
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Bus operations Table 7. Address insertion, x16 devices I/O8- Bus (1) cycle I/O15 th( Any additional address input cycles will be ignored. 2. The fifth ...
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NAND01G-B2B, NAND02G-B2C 5 Command set All bus write operations to the device are interpreted by the command interface. The commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when the Command Latch Enable signal ...
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Device operations 6 Device operations The following section gives the details of the device operations. 6.1 Read memory array At power-up the device defaults to read mode. To enter read mode from another mode the Read command must be issued, ...
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NAND01G-B2B, NAND02G-B2C Figure 6. Read operations I/O Address input 00h Command code 1. Highest address depends on device density. tBLBH1 30h Data output (sequentially) Command Busy code Device operations ai08657b 21/60 ...
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Device operations Figure 7. Random data output during sequential data output tBLBH1 (Read Busy time Address 30h I/O 00h inputs Cmd Cmd code code 5 Add cycles Row Add 1,2,3 Col Add 1,2 Main area 22/60 Busy 05h ...
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NAND01G-B2B, NAND02G-B2C 6.2 Cache read The cache read operation is used to improve the read throughput by reading data using the cache register. As soon as the user starts to read one page, the device automatically loads the next page ...
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Device operations 6.3 Page program The page program operation is the standard operation to program data to the memory array. Generally, the page is programmed sequentially, however the device does support random input within a page recommended to ...
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NAND01G-B2B, NAND02G-B2C Figure 9. Page program operation RB I/O 80h Page Program Setup Code Figure 10. Random data input during sequential data input RB Address I/O 80h Data Intput Inputs Cmd Code 5 Add cycles Row Add 1,2,3 Col Add ...
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Device operations 6.4 Copy back program The copy back program operation is used to copy the data stored in one page and reprogram it in another page. The copy back program operation does not require external memory and so the ...
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NAND01G-B2B, NAND02G-B2C Figure 11. Copy back program Source I/O 00h Add Inputs Read Code (Read Busy time) RB Figure 12. Page copy back program with random data input Source I/O 35h 00h Add Inputs Read Code tBLBH1 (Read Busy time) ...
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Device operations 6.5 Cache program The cache program operation is used to improve the programming throughput by programming data using the cache register. The cache program operation can only be used within one block. The cache register allows new data ...
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NAND01G-B2B, NAND02G-B2C 6.6 Block erase Erase operations are done one block at a time. An erase operation sets all of the bits in the addressed block to ‘1’. All previous data in the block is lost. An erase operation consists ...
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Device operations 6.8 Read status register The device contains a status register which provides information on the current or previous program or erase operation. The various bits in the status register convey information and errors on the operation. The status ...
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NAND01G-B2B, NAND02G-B2C 6.8.4 Cache program error bit (SR1) The cache program error bit can be used to identify if the previous page (page N-1) has been successfully programmed or not in a cache program operation. SR1 is set to ’1’ ...
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Device operations 6.9 Read electronic signature The device contains a manufacturer code and device code. To read these codes three steps are required: 1. One bus write cycle to issue the Read Electronic Signature command (90h) 2. One bus write ...
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NAND01G-B2B, NAND02G-B2C Table 16. Electronic signature byte/word 4 I/O I/O1-I/O0 I/O2 I/O7, I/O3 I/O5-I/O4 I/O6 Definition Page size (without spare area) Spare area size (byte / 512-byte) Minimum sequential access time Block size (without spare area) Organization Device operations Value ...
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Data protection 7 Data protection The device has hardware features to protect against program and erase operations. It features a Write Protect, WP, pin, which can be used to protect the device against program and erase operations recommended ...
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... To help integrate a NAND memory into an application, Numonyx can provide a file system OS native reference software, which supports the basic commands of file management. Contact the nearest Numonyx sales office for more details. ...
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Software algorithms Table 17. NAND flash failure modes Operation Erase Program Read Figure 15. Bad block management flowchart Figure 16. Garbage collection Valid page Invalid page 36/60 Procedure Block replacement Block replacement or ECC START Block Address = Block 0 ...
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... For every 2048 bits in the device it is recommended to implement 22 bits of ECC (16 bits for line parity plus 6 bits for column parity). An ECC model is available in VHDL or Verilog. Contact the nearest Numonyx sales office for more details. Software algorithms ...
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Software algorithms Figure 17. Error detection 8.6 Hardware simulation models 8.6.1 Behavioral simulation models Denali Software Corporation models are platform independent functional models designed to assist customers in performing entire system simulations (typical VHDL/Verilog). These models describe the logic behavior ...
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NAND01G-B2B, NAND02G-B2C 9 Program and erase times and endurance cycles The program and erase times and the number of program/erase cycles per block are shown in Table 18. Table 18. Program, erase times and program erase endurance cycles Parameters Page ...
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Maximum ratings 10 Maximum ratings Stressing the device above the ratings listed in cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the ...
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NAND01G-B2B, NAND02G-B2C 11 DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow, are derived from tests performed ...
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DC and AC parameters Figure 18. Equivalent testing circuit for AC characteristics measurement 42/ NAND flash C L GND GND NAND01G-B2B, NAND02G-B2C 2R ref 2R ref Ai11085 ...
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NAND01G-B2B, NAND02G-B2C Table 22. DC characteristics, 1.8 V devices Symbol Parameter I DD1 Operating current I DD2 I DD3 I Standby current (CMOS) DD5 I Input leakage current LI I Output leakage current LO V Input high voltage IH V ...
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DC and AC parameters Table 24. AC characteristics for command, address, data input Alt. Symbol symbol t Address Latch Low to Write Enable High ALLWH t ALS t Address Latch High to Write Enable High ALHWH Command Latch High to ...
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NAND01G-B2B, NAND02G-B2C Table 25. AC characteristics for operations Alt. Symbol symbol t Address Latch Low to ALLRL1 t AR Read Enable Low t ALLRL2 t t Ready/Busy High to Read Enable Low BHRL RR t BLBH1 t t BLBH2 PROG ...
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DC and AC parameters Figure 19. Command latch AC waveforms CL tCLHWH (CL Setup time) tELWH H(E Setup time tALLWH (ALSetup time) AL I/O Figure 20. Address latch AC waveforms CL tELWH (E Setup time) E tWLWH W ...
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NAND01G-B2B, NAND02G-B2C Figure 21. Data Input Latch AC waveforms CL E tALLWH (ALSetup time) AL tWLWH W (Data Setup time) I/O 1. Data in last is 2112 in x8 devices and 1056 in x16 devices. Figure 22. Sequential data output ...
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DC and AC parameters Figure 23. Read status register AC waveforms CL tCLHWH E tELWH W R (Data Setup time) I/O Figure 24. Read electronic signature AC waveforms I/O 90h Read Electronic Signature Command 1. ...
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NAND01G-B2B, NAND02G-B2C Figure 25. Page read operation AC waveforms CL E tWLWL Add.N Add.N Add.N I/O 00h cycle 1 cycle 2 cycle 3 Command Address N Input Code 1. A fifth address cycle is required for ...
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DC and AC parameters Figure 26. Page program AC waveforms CL E tWLWL (Write Cycle time Add.N Add.N I/O 80h cycle 1 cycle 2 RB Page Program Setup Code 1. A fifth address cycle is required for ...
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NAND01G-B2B, NAND02G-B2C Figure 27. Block erase AC waveforms CL E tWLWL (Write Cycle time Add. I/O 60h cycle 1 RB Block Erase Block Address Input Setup Command 1. Address cycle 3 is required for 2-Gbit devices only. ...
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DC and AC parameters Figure 29. Program/erase enable waveforms W tVHWH WP RB I/O Figure 30. Program/erase disable waveforms W tVLWH WP High RB I/O 11.1 Ready/Busy signal electrical characteristics Figure 32, Figure 31 signal. The value required for the ...
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NAND01G-B2B, NAND02G-B2C Figure 31. Ready/Busy AC waveform Figure 32. Ready/Busy load circuit ready busy DEVICE RB Open Drain Output and AC parameters AI07564B ...
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... 25°C. 11.2 Data protection The Numonyx NAND device is designed to guarantee data protection during power transitions detection circuit disables all NAND operations the V range from V DD low ( guarantee hardware protection during power transitions as shown in the below IL figure. Figure 34. Data protection ...
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... NAND01G-B2B, NAND02G-B2C 12 Package mechanical In order to meet environmental requirements, Numonyx offers these devices in ECOPACK® packages. ECOPACK® packages are lead-free. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label ...
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Package mechanical Figure 36. VFBGA63 9 active ball array, 0.80 mm pitch, package outline Drawing is not to scale Table 27. VFBGA63 9 ...
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NAND01G-B2B, NAND02G-B2C Figure 37. VFBGA63 active ball array, 0.80 mm pitch, package outline FD1 BALL "A1" 1. Drawing is not to scale Table 28. VFBGA63 ...
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... For NAND02G-B2C devices only. 3. For NAND01G-B2B devices only. Note: Devices are shipped from the factory with the memory content bits, in valid blocks, erased to ’1’. For further information on any aspect of this device, please contact your nearest Numonyx sales office. 58/60 NAND01G-B2B, NAND02G-B2C NAND02GR3B2C ...
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... Figure 11: Copy back t replaced by t WHBH2 BLBH5 program. Alt. symbol for BLBH4 operations. 5 Applied Numonyx branding. Revision history Changes removed. updated. Paragraph Section 6.2: Cache Section 8.2: NAND flash Figure 25: Page read operation AC Figure 26: Page program AC modified. Figure 9: Page program operation operations ...
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... NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems nuclear facility Numonyx may make changes to specifications and product descriptions at any time, without notice. ...