SC28L92A1A NXP Semiconductors, SC28L92A1A Datasheet - Page 20

• Manufacturer Part Number: SC28L92A1A
• Description: UART, DUAL, 3.3V OR 5V, SMD, 28L92
• Manufacturer: NXP Semiconductors

Specifications of SC28L92A1A

• No. Of Channels: 2
• Supply Voltage Range: 2.97V To 3.63V, 4.5V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: PLCC
• No. Of Pins: 44
• Svhc: No SVHC (18-Jun-2010)
• Operating: RoHS Compliant
• Data Rate: 230.4Kilobaud
• Uart Features: Programmable Channel Mode, Line Break Detection & Generation
• Rohs Compliant: Yes

NXP Semiconductors
SC28L92_7
Product data sheet
6.3.4 Receiver FIFO
6.3.5 Receiver status bits
6.3.6 Receiver reset and disable
The Rx FIFO consists of a First-In-First-Out (FIFO) stack with a capacity of 8 or 16
characters. Data is loaded from the receive shift register into the topmost empty position
of the FIFO. The RxRDY bit in the status register is set whenever one or more characters
are available to be read, and a FFULL status bit is set if all 8 or 16 stack positions are filled
with data. Either of these bits can be selected to cause an interrupt. A read of the Rx FIFO
outputs the data at the top of the FIFO. After the read cycle, the data FIFO and its
associated status bits (see
new data.
A disabled receiver with data in its FIFO may generate an interrupt (see
status bits remain active and its watchdog, if enabled, will continue to operate.
In addition to the data word, three status bits (parity error, framing error and received
break) are also appended to each data character in the FIFO. The overrun error, MR1[5],
is not FIFOed.
Status can be provided in two ways, as programmed by the error mode control bit in the
mode register. In the character mode, status is provided on a character-by-character
basis; the status applies only to the character at the top of the FIFO. In the block mode,
the status provided in the SR for these three bits is the logic OR of the status for all
characters coming to the top of the FIFO since the last reset error from the command
register was issued. In either mode reading the SR does not affect the FIFO. The FIFO is
popped only when the Rx FIFO is read. Therefore the status register should be read prior
to reading the FIFO.
If the FIFO is full when a new character is received, that character is held in the receive
shift register until a FIFO position is available. If an additional character is received while
this state exits, the contents of the FIFO are not affected; the character previously in the
shift register is lost and the overrun error status bit (SR[4]) will be set upon receipt of the
start bit of the new (overrunning) character.
The receiver can control the deactivation of RTS. If programmed to operate in this mode,
the RTSN output will be negated when a valid start bit was received and the FIFO is full.
When a FIFO position becomes available, the RTSN output will be reasserted (set LOW)
automatically. This feature can be used to prevent an overrun, in the receiver, by
connecting the RTSN output to the CTSN input of the transmitting device.
If the receiver is disabled, the FIFO characters can be read. However, no additional
characters can be received until the receiver is enabled again. If the receiver is reset, the
FIFO and all of the receiver status, and the corresponding output ports and interrupt are
reset. No additional characters can be received until the receiver is enabled again.
Receiver disable stops the receiver immediately. Data being assembled in the receiver
shift register is lost. Data and status in the FIFO is preserved and may be read. A
re-enable of the receiver after a disable will cause the receiver to begin assembling
characters at the next start bit detected.
Rev. 07 — 19 December 2007
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
Section
6.3.5) are popped thus emptying a FIFO position for
SC28L92
© NXP B.V. 2007. All rights reserved.
Section
6.3.5). Its
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