SC28L92A1A NXP Semiconductors, SC28L92A1A Datasheet - Page 18

• Manufacturer Part Number: SC28L92A1A
• Description: UART, DUAL, 3.3V OR 5V, SMD, 28L92
• Manufacturer: NXP Semiconductors

Specifications of SC28L92A1A

• No. Of Channels: 2
• Supply Voltage Range: 2.97V To 3.63V, 4.5V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: PLCC
• No. Of Pins: 44
• Svhc: No SVHC (18-Jun-2010)
• Operating: RoHS Compliant
• Data Rate: 230.4Kilobaud
• Uart Features: Programmable Channel Mode, Line Break Detection & Generation
• Rohs Compliant: Yes

NXP Semiconductors
SC28L92_7
Product data sheet
6.2.10 Output port
6.3.1 Transmitter
6.3 Operation
The output ports are controlled from six places: the OPCR, OPR, MR, Command, SOPR
and ROPR registers. The OPCR register controls the source of the data for the output
ports OP2 through OP7. The data source for output ports OP0 and OP1 is controlled by
the MR and CR registers. When the OPR is the source of the data for the output ports, the
data at the ports is inverted from that in the OPR register. The content of the OPR register
is controlled by the set output port bits command and the reset output bits command.
These commands are at 0xE and 0xF, respectively. When these commands are used,
action takes place only at the bit locations where ones exist. For example, a one in bit
location 5 of the data word used with the set output port bits command will result in OPR5
being set to one. The OP5 would then be set to zero (V
of the data word associated with the reset output ports bits command would set OPR5 to
zero and, hence, the pin OP5 to a one (V
These pins along with the IP pins and their change-of-state detectors are often used for
modem and DMA control.
The SC28L92 is conditioned to transmit data when the transmitter is enabled through the
command register. The SC28L92 indicates to the CPU that it is ready to accept a
character by setting the TxRDY bit in the status register. This condition can be
programmed to generate an interrupt request at OP6 or OP7 and INTRN. When the
transmitter is initially enabled the TxRDY and TxEMPT bits will be set in the status
register. When a character is loaded to the transmit FIFO the TxEMPT bit will be reset.
The TxEMPT will not set until: 1) the transmit FIFO is empty and the transmit shift register
has finished transmitting the stop bit of the last character written to the transmit FIFO, or
2) the transmitter is disabled and then re-enabled. The TxRDY bit is set whenever the
transmitter is enabled and the Tx FIFO is not full. Data is transferred from the holding
register to transmit shift register when it is idle or has completed transmission of the
previous character. Characters cannot be loaded into the Tx FIFO while the transmitter is
disabled.
The transmitter converts the parallel data from the CPU to a serial bit stream on the TxD
output pin. It automatically sends a start bit followed by the programmed number of data
bits, an optional parity bit, and the programmed number of stop bits. The least significant
bit is sent first. Following the transmission of the stop bits, if a new character is not
available in the Tx FIFO, the TxD output remains HIGH and the TxEMT bit in the Status
Register (SR) will be set to 1. Transmission resumes and the TxEMT bit is cleared when
the CPU loads a new character into the Tx FIFO.
If the transmitter is disabled it continues operating until the character currently being
transmitted and any characters in the Tx FIFO, including parity and stop bits, have been
transmitted. New data cannot be loaded to the Tx FIFO when the transmitter is disabled.
When the transmitter is reset it stops sending data immediately.
The transmitter can be forced to send a break (a continuous LOW condition) by issuing a
START BREAK command via the CR register. The break is terminated by a STOP BREAK
command or a transmitter reset.
Rev. 07 — 19 December 2007
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
DD
).
SS
). Similarly, a one in bit position 5
SC28L92
© NXP B.V. 2007. All rights reserved.
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