DK-DEV-5M570ZN Altera, DK-DEV-5M570ZN Datasheet - Page 124

• Manufacturer Part Number: DK-DEV-5M570ZN
• Description: KIT DEV MAX V 5M570Z
• Manufacturer: Altera
• Series: MAX® Vr
• Type: CPLDr

Specifications of DK-DEV-5M570ZN

• Contents: Board, Cable(s), Software and Documentation
• Silicon Manufacturer: Altera
• Core Architecture: CPLD
• Core Sub-architecture: MAX
• Silicon Core Number: 5M
• Silicon Family Name: MAX V
• Kit Contents: MAX V CPLD Development Board, USB Cable
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: 5M570ZF256
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2722

7–22
Figure 7–18. Timing Waveform for the ALTUFM_I2C Megafunction
Table 7–6. I2C Interface Timing Specification
MAX V Device Handbook
F
t
t
t
t
t
t
t
t
t
SCL:SDA
BUF
HD:STA
SU:STA
LOW
HIGH
HD:DAT
SU:DAT
SU:STO
SCL
Symbol
SDA
SCL
t
SU:STA
SCL clock frequency
SCL going low to SDA data out
Bus free time between a stop and start condition
(Repeated) start condition hold time
(Repeated) start condition setup time
SCL clock low period
SCL clock high period
SDA data in hold time
SDA data in setup time
STOP condition setup time
ALTUFM_I2C Interface Timing Specification
Figure 7–18
read/write mode.
Table 7–6
megafunction read/write mode.
Table 7–7. UFM Write Cycle Time
Table 7–8. UFM Erase Cycle Time
Write Cycle Time
Sector Erase
Cycle Time
Full Erase Cycle
Time
Parameter
Parameter
t
HD:STA
t
LOW
through
shows the timing waveform for the ALTUFM_I2C megafunction
Parameter
Table 7–8
t
HIGH
t
HD:DAT
Min
Min
—
—
—
t
list the timing specification needed for the ALTUFM_I2C
SCLSDA
t
SU:DAT
1,002
Max
Max
110
501
Min
4.7
4.7
4.7
—
—
20
4
4
0
4
Chapter 7: User Flash Memory in MAX V Devices
t
SU:STO
Unit
Unit
ms
ms
µs
January 2011 Altera Corporation
Max
100
15
—
—
—
—
—
—
—
—
Software Support for UFM Block
t
BUF
Unit
kHz
ns
µs
µs
µs
µs
µs
ns
ns
ns