PIC18F6680-I/L Microchip Technology, PIC18F6680-I/L Datasheet - Page 483

• Manufacturer Part Number: PIC18F6680-I/L
• Description: Microcontrollers (MCU) 64KB 3328 RAM 52 I/O
• Manufacturer: Microchip Technology

Specifications of PIC18F6680-I/L

• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.25 KB
• Interface Type: I2C/SPI/AUSART/CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 5
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Package / Case: PLCC-68
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Product Identification System ........................................... 487
Program Counter
Program Memory
Program Memory Modes
Program Memory Write Timing
Program Verification and
Programming, Device Instructions .................................... 365
PSP. See Parallel Slave Port.
PUSH ................................................................................ 394
PWM (CCP Module) ......................................................... 173
PWM (CCP Module) and Timer2
PWM (ECCP Module) ....................................................... 177
 2004 Microchip Technology Inc.
PCL, PCLATH and PCLATU
Instructions.................................................................. 57
Interrupt Vector ........................................................... 51
Map and Stack for
Map and Stack for
Memory Access for
Memory Maps for
Reset Vector ............................................................... 51
Extended Microcontroller ............................................ 93
Microcontroller ............................................................ 93
Microprocessor ........................................................... 93
Microprocessor with
Requirements............................................................ 432
Code Protection ........................................................ 359
Associated Registers ................................................ 359
Configuration Register
Data EEPROM Code
Memory Code Protection .......................................... 360
CCPR1H:CCPR1L Registers.................................... 177
CCPR1L:CCPR1H Registers.................................... 173
Duty Cycle......................................................... 173, 177
Example Frequencies/
Period................................................................ 173, 177
Registers Associated with PWM
Setup for PWM Operation......................................... 174
TMR2 to PR2 Match ................................. 162, 173, 177
Associated Registers ................................................ 174
Effects of a Reset...................................................... 187
Enhanced PWM Auto-Shutdown .............................. 184
Full-Bridge Application
Full-Bridge Mode....................................................... 181
Half-Bridge Mode ...................................................... 180
Half-Bridge Output Mode
Output Configurations ............................................... 177
Output Relationships
Registers............................................................. 56
Two-Word ........................................................... 58
PIC18F6585/8585............................................... 52
PIC18F6680/8680............................................... 52
PIC18F8X8X Modes ........................................... 52
PIC18F8X8X Modes ........................................... 53
Boot Block........................................................... 93
Protection.......................................................... 362
Protection.......................................................... 362
Resolutions ............................................... 174, 178
and Timer2........................................................ 187
Example ............................................................ 182
Direction Change .............................................. 182
Applications Example ....................................... 180
(Active-High State)............................................ 178
PIC18F6585/8585/6680/8680
Q
Q Clock ..................................................................... 173, 177
R
RAM. See Data Memory.
RC Oscillator....................................................................... 24
RCALL .............................................................................. 395
RCON Register................................................................. 123
RCSTA Register
Register File........................................................................ 59
Register File Summary ................................................. 67–77
Registers
Output Relationships
Programmable Dead-Band Delay............................. 184
PWM Direction Change (diagram)............................ 183
PWM Direction Change at Near 100%
Setup for Operation .................................................. 187
Start-up Considerations ............................................ 186
SPEN Bit................................................................... 229
ADCON0 (A/D Control 0).......................................... 249
ADCON1 (A/D Control 1).......................................... 250
ADCON2 (A/D Control 2).......................................... 251
BAUDCON (Baud Rate Control)............................... 232
BIE0 (Buffer Interrupt Enable 0) ............................... 322
BnCON (TX/RX Buffer n Control,
BnCON (TX/RX Buffer n Control,
BnDLC (TX/RX Buffer n Data Length
BnDLC (TX/RX Buffer n Data Length
BnDm (TX/RX Buffer n Data Field Byte m
BnDm (TX/RX Buffer n Data Field Byte m
BnEIDH (TX/RX Buffer n Extended
BnEIDH (TX/RX Buffer n Extended
BnEIDL (TX/RX Buffer n Extended
BnEIDL (TX/RX Buffer n Extended
BnSIDH (TX/RX Buffer n Standard
BnSIDH (TX/RX Buffer n Standard
BnSIDL (TX/RX Buffer n Standard
(Active-Low State) ............................................ 179
Duty Cycle (diagram)........................................ 183
Receive Mode) ................................................. 297
Transmit Mode) ................................................ 298
Code in Receive Mode) .................................... 304
Code in Transmit Mode) ................................... 305
in Receive Mode).............................................. 303
in Transmit Mode)............................................. 303
Identifier, High Byte in
Receive Mode) ................................................. 301
Identifier, High Byte in
Transmit Mode) ................................................ 301
Identifier, Low Byte in
Receive Mode) ................................................. 302
Identifier, Low Byte in
Transmit Mode) ................................................ 302
Identifier, High Byte in
Receive Mode) ................................................. 299
Identifier, High Byte in
Transmit Mode) ................................................ 299
Identifier, Low Byte in
Receive Mode) ................................................. 300
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