PIC18F6680-I/L Microchip Technology, PIC18F6680-I/L Datasheet - Page 383

Microcontrollers (MCU) 64KB 3328 RAM 52 I/O

PIC18F6680-I/L

Manufacturer Part Number
PIC18F6680-I/L
Description
Microcontrollers (MCU) 64KB 3328 RAM 52 I/O
Manufacturer
Microchip Technology
Datasheet

Specifications of PIC18F6680-I/L

Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.25 KB
Interface Type
I2C/SPI/AUSART/CAN
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
53
Number Of Timers
5
Operating Supply Voltage
4.2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
12-ch x 10-bit
Program Memory Type
Flash
Program Memory Size
64 KB
Package / Case
PLCC-68
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F6680-I/L
Manufacturer:
RUBYCON
Quantity:
46 000
Part Number:
PIC18F6680-I/L
Manufacturer:
MICROCH
Quantity:
20 000
CLRF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
 2004 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
Decode
FLAG_REG
FLAG_REG
Q1
register ‘f’
Clear f
[ label ] CLRF
0
a
000h
1
Z
Clears the contents of the specified
register. If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
1
1
CLRF
Read
0110
Q2
=
=
f
[0,1]
Z
255
0x5A
0x00
f
101a
FLAG_REG,1
Process
Data
Q3
f [,a]
ffff
register ‘f’
PIC18F6585/8585/6680/8680
Write
Q4
ffff
CLRWDT
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
WDT Counter
WDT Counter
WDT Postscaler
TO
PD
Q1
operation
Clear Watchdog Timer
[ label ] CLRWDT
None
000h
000h
1
1
TO, PD
CLRWDT instruction resets the
Watchdog Timer. It also resets the
postscaler of the WDT. Status bits
TO and PD are set.
1
1
CLRWDT
0000
No
Q2
TO,
PD
=
=
=
=
=
WDT,
WDT postscaler,
0000
?
0x00
0
1
1
Process
Data
Q3
DS30491C-page 381
0000
operation
No
Q4
0100

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