PIC18F6680-I/L Microchip Technology, PIC18F6680-I/L Datasheet - Page 186

• Manufacturer Part Number: PIC18F6680-I/L
• Description: Microcontrollers (MCU) 64KB 3328 RAM 52 I/O
• Manufacturer: Microchip Technology

Specifications of PIC18F6680-I/L

• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.25 KB
• Interface Type: I2C/SPI/AUSART/CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 5
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Package / Case: PLCC-68
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F6585/8585/6680/8680
16.2.6
In half-bridge applications where all power switches are
modulated at the PWM frequency at all times, the
power switches normally require more time to turn off
than to turn on. If both the upper and lower power
switches are switched at the same time (one turned on
and the other turned off), both switches may be on for
a short period of time until one switch completely turns
off. During this brief interval, a very high current (shoot-
through current) may flow through both power
switches, shorting the bridge supply. To avoid this
potentially destructive shoot-through current from flow-
ing during switching, turning on either of the power
switches is normally delayed to allow the other switch
to completely turn off.
In the Half-Bridge Output mode, a digitally pro-
grammable dead-band delay is available to avoid
shoot-through current from destroying the bridge
power switches. The delay occurs at the signal
transition from the non-active state to the active state.
See Figure 16-5 for an illustration. The lower seven bits
of the ECCP1DEL register (Register 16-2) set the
delay period in terms of microcontroller instruction
cycles (T
16.2.7
When the CCP1 is programmed for any of the
enhanced PWM modes, the active output pins may be
configured for auto-shutdown. Auto-shutdown immedi-
ately places the enhanced PWM output pins into a
defined shutdown state when a shutdown event
occurs.
REGISTER 16-2:
DS30491C-page 184
CY
bit 7
bit 6-0
PROGRAMMABLE
DEAD-BAND DELAY
ENHANCED PWM
AUTO-SHUTDOWN
or 4 T
OSC
).
ECCP1DEL: ECCP1 DELAY REGISTER
bit 7
PRSEN: PWM Restart Enable bit
1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event
0 = Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM
PDC<6:0>: PWM Delay Count bits
Number of F
transition active and the actual time it transitions active.
Legend:
R = Readable bit
- n = Value at POR
PRSEN
R/W-0
goes away; the PWM restarts automatically
OSC
R/W-0
PDC6
/4 (4 * T
OSC
R/W-0
PDC5
) cycles between the scheduled time when a PWM signal should
W = Writable bit
‘1’ = Bit is set
R/W-0
PDC4
A shutdown event can be caused by either of the two
comparator modules or a low level on the RB0 pin (or
any combination of these three sources). The compar-
ators may be used to monitor a voltage input propor-
tional to a current being monitored in the bridge circuit.
If the voltage exceeds a threshold, the comparator
switches state and triggers a shutdown. Alternatively, a
low digital signal on the RB0 pin can also trigger a
shutdown. The auto-shutdown feature can be disabled
by not selecting any auto-shutdown sources. The
auto-shutdown sources to be used are selected using
the ECCPAS2:ECCPAS0 bits (bits <6:4> of the
ECCP1AS register).
When a shutdown occurs, the output pins are asyn-
chronously placed in their shutdown states, specified
by the PSSAC1:PSSAC0 and PSSBD1:PSSBD0 bits
(ECCP1AS<3:0>). Each pin pair (P1A/P1C and P1B/
P1D) may be set to drive high, drive low, or be tri-stated
(not driving). The ECCPASE bit (ECCP1AS<7>) is also
set to hold the enhanced PWM outputs in their
shutdown states.
The ECCPASE bit is set by hardware when a shutdown
event occurs. If automatic restarts are not enabled, the
ECCPASE bit is cleared by firmware when the cause of
the shutdown clears. If automatic restarts are enabled,
the ECCPASE bit is automatically cleared when the
cause of the auto-shutdown has cleared.
If the ECCPASE bit is set when a PWM period begins,
the PWM outputs remain in their shutdown state for that
entire PWM period. When the ECCPASE bit is cleared,
the PWM outputs will return to normal operation at the
beginning of the next PWM period.
Note:
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PDC3
Writing to the ECCPASE bit is disabled
while a shutdown condition is active.
R/W-0
PDC2
 2004 Microchip Technology Inc.
x = Bit is unknown
R/W-0
PDC1
R/W-0
PDC0
bit 0