PIC18F6680-I/L Microchip Technology, PIC18F6680-I/L Datasheet - Page 244

• Manufacturer Part Number: PIC18F6680-I/L
• Description: Microcontrollers (MCU) 64KB 3328 RAM 52 I/O
• Manufacturer: Microchip Technology

Specifications of PIC18F6680-I/L

• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.25 KB
• Interface Type: I2C/SPI/AUSART/CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 5
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Package / Case: PLCC-68
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F6585/8585/6680/8680
18.2.4
During Sleep mode, all clocks to the USART are
suspended. Because of this, the Baud Rate Generator
is inactive and a proper byte reception cannot be per-
formed. The auto-wake-up feature allows the controller
to wake-up due to activity on the RX/DT line while the
USART is operating in Asynchronous mode.
The auto-wake-up feature is enabled by setting the
WUE bit (BAUDCON<1>). Once set, the typical receive
sequence on RX/DT is disabled and the USART
remains in an Idle state monitoring for a wake-up event
independent of the CPU mode. A wake-up event con-
sists of a high-to-low transition on the RX/DT line. (This
coincides with the start of a sync break or a wake-up
signal character for the LIN protocol.)
Following a wake-up event, the module generates an
RCIF interrupt. The interrupt is generated synchro-
nously to the Q clocks in normal operating modes
(Figure 18-7) and asynchronously, if the device is in
Sleep mode (Figure 18-8). The interrupt condition is
cleared by reading the RCREG register.
The WUE bit is automatically cleared once a low-to-
high transition is observed on the RX line following the
wake-up event. At this point, the USART module is in
Idle mode and returns to normal operation. This signals
to the user that the sync break event is over.
18.2.4.1
Since auto-wake-up functions by sensing rising edge
transitions on RX/DT, information with any state changes
before the Stop bit may signal a false end-of-character
FIGURE 18-7:
FIGURE 18-8:
DS30491C-page 242
RX/DT Line
Note:
Note 1:
RX/DT Line
WUE bit
WUE bit
OSC1
OSC1
2:
RCIF
RCIF
The USART remains in Idle while the WUE bit is set.
This sequence should not depend on the presence of Q clocks.
If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur while the stposc signal is still active.
The USART remains in Idle while the WUE bit is set.
AUTO-WAKE-UP ON SYNC BREAK
CHARACTER
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Special Considerations Using
Auto-Wake-up
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Bit Set by User
Bit Set by User
Sleep Command Executed
AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION
AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP
Q1
Sleep Ends
and cause data or framing errors. To work properly,
therefore, the initial character in the transmission must
be all ‘0’s. This can be 00h (8 bytes) for standard RS-232
devices or 000h (12 bits) for LIN bus.
Oscillator start-up time must also be considered,
especially in applications using oscillators with longer
start-up intervals (i.e., XT or HS mode). The sync break
(or wake-up signal) character must be of sufficient
length and be followed by a sufficient interval to allow
enough time for the selected oscillator to start and
provide proper initialization of the USART.
18.2.4.2
The timing of WUE and RCIF events may cause some
confusion when it comes to determining the validity of
received data. As noted, setting the WUE bit places the
USART in an Idle mode. The wake-up event causes a
receive interrupt by setting the RCIF bit. The WUE bit
is cleared after this when a rising edge is seen on
RX/DT. The interrupt condition is then cleared by read-
ing the RCREG register. Ordinarily, the data in RCREG
will be dummy data and should be discarded.
The fact that the WUE bit has been cleared (or is still
set) and the RCIF flag is set should not be used as an
indicator of the integrity of the data in RCREG. Users
should consider implementing a parallel method in
firmware to verify received data integrity.
To assure that no actual data is lost, check the RCIDL
bit to verify that a receive operation is not in process. If
a receive operation is not occurring, the WUE bit may
then be set just prior to entering the Sleep mode.
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Cleared due to User Read of RCREG
Cleared due to User Read of RCREG
Special Considerations Using
the WUE Bit
 2004 Microchip Technology Inc.
Note 1
Auto-Cleared
Auto-Cleared