PIC18F6680-I/L Microchip Technology, PIC18F6680-I/L Datasheet - Page 376

• Manufacturer Part Number: PIC18F6680-I/L
• Description: Microcontrollers (MCU) 64KB 3328 RAM 52 I/O
• Manufacturer: Microchip Technology

Specifications of PIC18F6680-I/L

• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.25 KB
• Interface Type: I2C/SPI/AUSART/CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 5
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Package / Case: PLCC-68
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F6585/8585/6680/8680
BCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS30491C-page 374
Q Cycle Activity:
Before Instruction
After Instruction
Decode
FLAG_REG = 0xC7
FLAG_REG = 0x47
Q1
register ‘f’
Bit Clear f
[ label ] BCF
0
0
a
0
None
Bit ‘b’ in register ‘f’ is cleared. If ‘a’
is ‘0’, the Access Bank will be
selected, overriding the BSR value.
If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
1
1
BCF
Read
1001
Q2
f
b
[0,1]
f<b>
255
7
FLAG_REG,
bbba
Process
Data
Q3
f,b[,a]
ffff
7, 0
register ‘f’
Write
Q4
ffff
BN
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If Jump:
If No Jump:
Before Instruction
After Instruction
operation
Decode
Decode
PC
If Negative =
If Negative =
No
Q1
Q1
PC
PC
Read literal
Read literal
operation
Branch if Negative
[ label ] BN
-128
if negative bit is ‘1’
(PC) + 2 + 2n
None
If the Negative bit is ‘1’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
1
1(2)
HERE
=
=
=
1110
No
Q2
Q2
‘n’
‘n’
address (HERE)
1;
address (Jump)
0;
address (HERE+2)
 2004 Microchip Technology Inc.
n
127
0110
operation
BN
Process
Process
Data
Data
n
No
Q3
Q3
PC
Jump
nnnn
Write to PC
operation
operation
No
No
Q4
Q4
nnnn