HFIXF1110CC.B3-998844 Cortina Systems Inc, HFIXF1110CC.B3-998844 Datasheet - Page 85

• Manufacturer Part Number: HFIXF1110CC.B3-998844
• Description: IC ETHERNET MAC 10PORT 552-CBGA
• Manufacturer: Cortina Systems Inc

Specifications of HFIXF1110CC.B3-998844

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-4.2
• Voltage - Supply: 1.8 V, 2.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1010

IXF1110 MAC
Datasheet
250210, Revision 11.0
13 April 2009
Figure 25
5.6.2
Table 28
Cortina Systems
Figure 25
CPU Interface Inputs/Outputs
Functional Description
The CPU interface is designed for a generic 32-bit asynchronous CPU bus. The bus is a
32-bit data bus only and has an 11-bit address bus.
The IXF1110 MAC external CPU interface is asynchronous and has no clock. This allows
flexibility for CPU selection.The interface to all IXF1110 MAC registers is synchronous to
125 MHz internally.
In some applications, synchronous-to-asynchronous glue logic is required between the
IXF1110 MAC and the system CPU. This glue logic must be designed so that the
IXF1110 MAC Read and Write access times are not violated. It may be possible to interface
without glue logic if the CPU can meet the timing seen in
Asynchronous Interface, on page
page
CPU Interface Signals
UPX_ADD[10:0]
Internal IXF1110 MAC registers and counters are selected using the 11-bit address bus
input provided at the CPU interface. This address must be stable for the entire cycle.
®
UPX_ADD[10:0]
UPX_CS_L
UPX_DATA[31:0]
UPX_WR_L
UPX_RD_L
UPX_RDY_L
• Optical Module Block
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
87, and
Name
illustrates the I/O for the CPU interface on the IXF1110 MAC.
UPX_RDY_L
UPX_WR_L
UPX_RD_L
UPX_CS_L
UPX_ADDR[10:0]
UPX_DATA[31:0]
Table 39, CPU Timing Parameters, on page 106
Input
Input
Bi_Dir
Input
Input
Output
Direction
87,
Figure 27, Write Timing – Asynchronous Interface, on
11
32
CMOS 2.5 V
CMOS 2.5 V
CMOS 2.5 V
CMOS 2.5 V
CMOS 2.5 V
CMOS 2.5 V
Standard
Figure 26, Read Timing –
CPU Interface
Address bus
Chip Select Signal
Bi-directional data bus
Write Strobe
Read Strobe
Cycle complete indicator
Description
B3379-01
5.6 CPU Interface
Page 85