HFIXF1110CC.B3-998844 Cortina Systems Inc, HFIXF1110CC.B3-998844 Datasheet - Page 62

• Manufacturer Part Number: HFIXF1110CC.B3-998844
• Description: IC ETHERNET MAC 10PORT 552-CBGA
• Manufacturer: Cortina Systems Inc

Specifications of HFIXF1110CC.B3-998844

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-4.2
• Voltage - Supply: 1.8 V, 2.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1010

IXF1110 MAC
Datasheet
250210, Revision 11.0
13 April 2009
5.2.2.9
5.2.2.10
5.2.3
5.2.3.1
5.2.3.2
Cortina Systems
MaxBurst1
MaxBurst1 is an RX SPI4-2 parameter specifying the maximum number of 16 byte blocks
that may be transmitted when the associated FIFO status indicates “starving”. Bits 24 to 16
of the SPI4-2 RX Burst Size Register specify this parameter. The default value for
MaxBurst1 is 0x006, indicating a MaxBurst1 of 96 bytes [see
($ 0x700), on page
MaxBurst2
MaxBurst2 is an RX SPI4-2 parameter specifying the maximum number of 16 byte blocks
that may be transmitted when the associated FIFO status indicates “hungry”. Bits 8 to 0 of
the SPI4-2 RX Burst Size Register specify this parameter. The default value for MaxBurst2
is 0x002, indicating a MaxBurst2 of 32 bytes (see
page
Dynamic Phase Alignment Training Sequence (Data Path
De-skew)
Training at Start-up
The SPI4-2 Specification states that on power-up or after a reset, the training sequence (as
defined in the SPI4-2 Specification) is sent indefinitely by the source side until it receives
valid FIFO status on the FIFO bus. The specification also states that it is possible for the
bus de-skew to be completed after one training sequence takes place. It is unlikely that the
bus can be de-skewed in a single training sequence because of the presence of both
random and deterministic jitter. The only way to account for the random element is to
determine an average over repeated training sequences. Since the required number of
repeats is dependent on several characteristics of the system in which the IXF1110 MAC is
being used, power on training (or training following loss of synchronization) will continue
until synchronization is achieved and the calendar is provisioned. The length of power on
training will not be a fixed number of repeats.
The number of training sequence repeats could be fairly large (16, 32, or 64). If this is
necessary every time training is required, a significant use of interface bandwidth is needed
just to train and de-skew the data path. This is only done at power-up or reset for an optimal
starting point interface. After this, periodic training provides a better adjustment and a
substantially lower bandwidth overhead.
Periodic Training
A scheduled training sequence is sent at least once every pre-configured bounded interval
(DATA_MAX_T) on both the transmit and receive paths. These training sequences are used
by the receiving end of each interface for de-skewing bit arrival times on the data and
control lines. The sequence allows the receiving end to correct for relative skew difference
of up to +/- 1 bit time. The training sequence consists of one (1) idle control word followed
by one or more repetitions of a 20- word training pattern consisting of 10 (repeated)
training-control words followed by 10 (repeated) training-data words.
The initial idle control word removes dependencies of the DIP-4 in the training control words
from preceding data words. Assuming a maximum of +/- bit time alignment jitter on each
line, and a maximum of +/- bit time relative skew between lines, there are at least eight bit
times when a receiver can detect a training control word prior to de-skew. The training data
word is chosen to be orthogonal to the training control word. In the absence of bit errors in
the training pattern, a receiver should be able successfully to de-skew the data and control
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
162).
162].
SPI4-2 RX Burst Size ($ 0x700), on
5.2 System Packet Interface Level 4
SPI4-2 RX Burst Size
Page 62
Phase 2