HFIXF1110CC.B3-998844 Cortina Systems Inc, HFIXF1110CC.B3-998844 Datasheet - Page 65

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HFIXF1110CC.B3-998844

Manufacturer Part Number
HFIXF1110CC.B3-998844
Description
IC ETHERNET MAC 10PORT 552-CBGA
Manufacturer
Cortina Systems Inc

Specifications of HFIXF1110CC.B3-998844

Controller Type
Ethernet Controller, MAC
Interface
SPI-4.2
Voltage - Supply
1.8 V, 2.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
575-BCBGA Exposed Pad (552 Bumps)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Other names
1008-1010

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Price
Part Number:
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Manufacturer:
Cortina Systems Inc
Quantity:
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HFIXF1110CC.B3-998844
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HFIXF1110CC.B3-998844
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Quantity:
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IXF1110 MAC
Datasheet
250210, Revision 11.0
13 April 2009
Figure 15
Cortina Systems
Example of DIP-2 Encoding
When the parity bits mimic the “1 1” pattern, the receiving end still frames successfully by
syncing onto the last cycle in a repeated “1 1” pattern, and by making use of the configured
sequence length when searching for the framing pattern.
To permit more efficient FIFO utilization, the MaxBurst1 and MaxBurst2 credits are granted
and consumed in increments of 16-byte blocks. For any given port, these credits
correspond to the most recently received FIFO status. They are not cumulative and
supersede previously granted credits for the given port. A burst transfer shorter than
16 bytes (for example, an end-of-packet fragment) consumes an entire 16-byte credit.
A continuous stream of repeated “1 1” framing patterns indicates a disabled status link. For
example, it may be sent to indicate that the data path de-skew is not yet completed or
confirmed. When a repeated “1 1” pattern is detected, all outstanding credits are cancelled
and set to zero.
®
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
5
6
7
8
9
2
3
4
1
1
1
0
1
0
0
0
1
0
0
a
0
1
0
0
0
0
0
0
0
1
1
b
DIP2 Parity Bits
to 2
to 3
to 4
to 5
to 6
to 7
to 8
to 9
(DIP2[1:0])
Framing Pattern
2nd Status Word
3rd Status Word
1st Status Word
4th Status Word
5th Status Word
6th Status Word
7th Status Word
8th Status Word
DIP2 Parity Bits
(not included
calculations)
parity in
5.2 System Packet Interface Level 4
a and b are set to 1
during enccoding
Page 65
Phase 2

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