HFIXF1110CC.B3-998844 Cortina Systems Inc, HFIXF1110CC.B3-998844 Datasheet - Page 167

• Manufacturer Part Number: HFIXF1110CC.B3-998844
• Description: IC ETHERNET MAC 10PORT 552-CBGA
• Manufacturer: Cortina Systems Inc

Specifications of HFIXF1110CC.B3-998844

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-4.2
• Voltage - Supply: 1.8 V, 2.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1010

IXF1110 MAC
Datasheet
250210, Revision 11.0
13 April 2009
Table 109
Table 110
Cortina Systems
Optical Module Control Ports 0-9 ($ 0x79A)
I
®
Register Description: This register provides access to optical module interrupt enables and
sets the TX_DISABLE outputs.
1. R = Read Only; CoR = Clear on Read; W = Write only; R/W = Read/Write
Register Description: This register controls I
1. R = Read Only; CoR = Clear on Read; W = Write only; R/W = Read/Write
2
C Control Ports 0-9 ($ 0x79B) (Sheet 1 of 2)
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
31:13
31:29
19:16
Bit
9:0
Bit
12
10
28
27
26
25
24
23
22
21
20
11
Reserved
RX_LOS_En
TX_FAULT_En
MOD_DEF_En
TX_DISABLE_9:0 TX_DISABLE outputs for Ports 0-9
Reserved
Port Address
Error
WP_Err
no_ack-err
I
I
Reserved
Write Complete
Reserved
Read Valid
Port Address
Select 3:0
2
2
CEnable
C Start
Name
Name
Reserved
Port Address Error is set to 1 when an access is
requested to port address > 0x9.
Write Protect error is set to 1 when a write access is
requested to Device ID = 0xA and Register Address
[10:8] = 0. This address combination is used solely
for the read only optical module.
This bit is set to 1 when a optical module has failed
to assert an acknowledge cycle. This signal should
be used to validate the data being read. Data is only
valid if this bit is equal to zero.
Enables device wide I
I
clear on read.
Reserved
Write Complete is set to a 1 when the byte write
cycle has completed.
Reserved
Read Valid is set to a 1 when valid data is available
in the DataRead7:0 field.
IXF1110 MAC port address to be accessed
2
C Start = 1 will initiate the I
Reserved
Enable for RX_LOS_Int operation
0 = Disabled
1 = Enabled
Enable for TX_FAULT_Int operation
0 = Disabled
1 = Enabled
Enable for MOD_DEF_Int operation
0 = Disabled
1 = Enabled
2
C Reads and Writes.
Description
Description
2
C Accesses (Enabled = 1)
2
C cycle. This bit is
Type
Type
R/W
CoR
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
1
1
8.5 Memory Map
0x00000000
0x00000000
0000000000
0000000000
000000000
Default
Default
000
0x0
0
0
0
0
0
0
0
0
0
0
0
0
Page 167