HFIXF1110CC.B3-998844 Cortina Systems Inc, HFIXF1110CC.B3-998844 Datasheet - Page 82

• Manufacturer Part Number: HFIXF1110CC.B3-998844
• Description: IC ETHERNET MAC 10PORT 552-CBGA
• Manufacturer: Cortina Systems Inc

Specifications of HFIXF1110CC.B3-998844

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-4.2
• Voltage - Supply: 1.8 V, 2.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1010

IXF1110 MAC
Datasheet
250210, Revision 11.0
13 April 2009
Note:
Figure 24
Table 25
5.5.6
5.5.6.1
Cortina Systems
The LED_LATCH signal is required in Mode 1, and is used to latch the data shifted into the
shift register chain into the output latches of the 74HC595 device. As seen in
LED_LATCH signal is active High during the Low period on the 36th LED_CLK cycle. This
avoids any possibility of trying to latch data as it is shifting through the register.
When this operation mode is implemented on a board with a shift register chain containing
three 74HC595 devices, the LED DATA bit 1 is output on Shift Register bit 1, and so on up
the chain. Only Shift Register bits 31 and 32 do not contain valid data. The actual data
shown in
36-bit data chain is built up as follows:
The LED_DATA signal is now inverted from the state in Mode 0.
Mode 1 Timing
Mode 1 Clock Cycle to Data Bit Relationship
Power-On, Reset, and Initialization
The LED interface is disabled at power-on or reset. The system software controller must
enable the LED interface. The internal state machines and output pins are held in reset until
the full IXF1110 MAC configuration is completed.
Enabling the LED Interface
LED Control ($ 0x509), on page
interface. This is done by setting the LED_ENABLE bit to a logic 1. The power-on default for
this bit is Logic 0.
®
LED_CLK
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
CYCLE
34:36
4:33
LED_LATCH
2:3
LED_DATA
1
LED_CLK
Figure 24
START BIT
PAD BITS
LED DATA
1-30
PAD BITS
LED_DATA
NAME
consists of a 36-bit chain, of which 30 bits are valid LED DATA. The
1
2
This bit has no meaning in Mode 1 operation and is shifted out of the 32-stage
shift register chain before the LED_LATCH signal is asserted.
These bits have no meaning in Mode 1 operation and are shifted out of the
32-stage shift register chain before the LED_LATCH signal is asserted.
These bits are the actual data to be transmitted to the 32-stage shift register
chain. The decode for each bit in each mode is defined in
to Data Bit Relationship, on page
The data is INVERTED. Logic 1 (LED ON) = Low.
These bits have no meaning in Mode 1 operation and are latched into positions
31 and 32 in the shift register chain. These bits are not considered as valid data
and should be ignored. They should always be a Logic 0 = High.
3
4
1
143: This register must be set to globally enable LED
26
23 24 25 26 27 28 29 30
27
28
LED_DATA DESCRIPTION
29
82.
30
31
32
33
34
Mode 1 Clock Cycle
35
5.5 LED Interface
Figure
36
24, the
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