HFIXF1110CC.B3-998844 Cortina Systems Inc, HFIXF1110CC.B3-998844 Datasheet - Page 55

• Manufacturer Part Number: HFIXF1110CC.B3-998844
• Description: IC ETHERNET MAC 10PORT 552-CBGA
• Manufacturer: Cortina Systems Inc

Specifications of HFIXF1110CC.B3-998844

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-4.2
• Voltage - Supply: 1.8 V, 2.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1010

IXF1110 MAC
Datasheet
250210, Revision 11.0
13 April 2009
Table 17
5.2.1
Note:
Note:
Cortina Systems
SPI4-2 Interface Signal Summary (Sheet 2 of 2)
Data Path
Transfer of complete packets or shorter bursts is controlled by the programmed MaxBurst1
or MaxBurst2 in conjunction with the FIFO status bus. The maximum configured payload
data transfer size must be a multiple of 16 bytes. Control words are inserted between burst
transfers only. Once a transfer begins, data words are sent uninterrupted until an
end-of-packet, or until a multiple of 16 bytes is reached as programmed in MaxBurst1 and
MaxBurst2. The interval between the end of a given transfer and the next payload control
word (marking the start of another transfer) consists of zero or more idle control words
and/or training patterns.
The system designer should be aware that the MAC Transfer Threshold Register must be
set to a value which exceeds the MaxBurst1 setting of the network processor or ASIC.
Otherwise, a TX FIFO under-run may result.
The minimum and maximum supported packet lengths are determined by the application.
Because the IXF1110 MAC is targeted at the Ethernet environment, the minimum frame
size is 64 bytes and the maximum frame size is 1522 bytes for VLAN packets (1518 bytes
for non-VLAN packets). For larger frames, adjust the value of
($ Port_Index + 0x0F), on page
start-of-packets must occur not less than eight cycles apart, where a cycle is one control or
data word. The gap between shorter packets is filled with idle control words.
Data packets with frame lengths less than 64 bytes should not be transferred to the
IXF1110 MAC unless packet padding is enabled. If this rule is disregarded, unwanted
fragments may be generated on the network at the SerDes interface.
Figure 10 on page 56
transitions. The states correspond to the type of words transferred on the data path.
Transitions from the “Data Burst” state (to “Payload Control” or “Idle Control”) are possible
only on the integer multiples of eight cycles (corresponding to multiples of 16-byte
segmentations) or upon end-of-packet. A data burst must immediately follow a payload
control word on the next cycle. Arcs not annotated correspond to single cycles.
In the IXF1110 MAC, the RX FIFO Status channel operates in a “pessimistic mode.” It is
termed as pessimistic because it has the longest latency and largest impact on usable
bandwidth. However, as a DIP-2 check error is a rare event, there will be no ‘real world’
effect on bandwidth utilization and no possibility of data loss. For example, if there is a
DIP-2 check error found, all previously granted credits are cancelled and the internal status
for each port is set to SATISFIED. Any current data burst in transmission is completed. No
®
RDCLK_P/N
RCTL_P/N
RSCLK
RSTAT1, RSTAT0
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
Signal Name
Receive Data Clock: Differential LVDS clock associated with RDAT[15:0] and RCTL.
Data and control lines are driven off the rising and falling edges of the clock.
Internally terminated differentially with 100 Ω
Receive Control: RCTL is High when a control word is present on RDAT[15:0].
Otherwise, RCTL is Low.
Internally terminated differentially with 100 Ω
Receive Status Clock: LVTTL clock associated with RSTAT[1:0].
Receive FIFO Status: LVTTL lines used to carry round-robin FIFO status information,
along with associated error detection and framing.
shows cycle-by-cycle behavior of the data path for valid state
127. For ease of implementation, successive
Signal Description
5.2 System Packet Interface Level 4
Max Frame Size
Page 55
Phase 2