XQ2V1000-4BG575N Xilinx Inc, XQ2V1000-4BG575N Datasheet - Page 78

• Manufacturer Part Number: XQ2V1000-4BG575N
• Description: FPGA 650MHZ CMOS1.5V 575-P
• Manufacturer: Xilinx Inc
• Series: QPro™ Virtex™-IIr

Specifications of XQ2V1000-4BG575N

• Number Of Labs/clbs: 1280
• Total Ram Bits: 737280
• Number Of I /o: 328
• Number Of Gates: 100000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -55°C ~ 125°C
• Package / Case: 575-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Other names: Q5801737

Table 71: QPro Virtex-II Pin Definitions (Cont’d)
DS122 (v2.0) December 21, 2007
Product Specification
Notes:
1.
Dedicated Pins
Other Pins
CCLK
PROG_B
DONE
M2, M1, M0
HSWAP_EN
TCK
TDI
TDO
TMS
PWRDWN_B
DXN, DXP
V
RSVD
V
V
V
GND
All dedicated pins (JTAG and configuration) are powered by V
BATT
CCO
CCAUX
CCINT
Pin Name
R
(1)
Input/Output
Input
Input/Output
Input
Input
Output
Input
Input
(unsupported)
N/A
Input
N/A
Input
Input
Input
Input
Input
Input
Direction
Configuration clock. Output in Master mode or Input in Slave mode.
Active-Low asynchronous reset to configuration logic. This pin has a permanent weak pull-up
resistor.
DONE is a bidirectional signal with an optional internal pull-up resistor. As an output, this pin
indicates completion of the configuration process. As an input, a Low level on DONE can be
configured to delay the start-up sequence.
Configuration mode selection.
Boundary Scan Data Input.
Boundary Scan Data Output.
Boundary Scan Mode Select.
Active-Low power-down pin (unsupported). Driving this pin Low can adversely affect device
operation and configuration. PWRDWN_B is internally pulled High, which is its default state. It
does not require an external pull-up.
Temperature-sensing diode pins (Anode: DXP, Cathode: DXN).
Decryptor key memory backup supply. (Do not connect if battery is not used.)
Reserved pin – do not connect.
Power-supply pins for the output drivers (per bank).
Power-supply pins for auxiliary circuits.
Power-supply pins for the internal core logic.
Ground.
Enable I/O pullups during configuration.
Boundary Scan Clock.
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CCAUX
(independent of the bank V
Description
QPro Virtex-II 1.5V Platform FPGAs
CCO
voltage).
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